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參數(shù)資料
| 型號： | LM1229YA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運動控制電子 |
| 英文描述： | I2C Compatible CMOS TV RGB and Deflection Processor |
| 中文描述： | WAVEFORM GENERATION, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數(shù)： | 8/27頁 |
| 文件大?。?/td> | 969K |
| 代理商： | LM1229YA |
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Note 13:
Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200 pF cap is charged to the specific voltage, then discharged directly into the
IC with no external series resistor (resistance of discharge path must be under 50
).
Note 14:
Measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation. Terminate the undriven amplifier
inputs to simulate generator loading. Repeat test at f
IN
= 10 MHz for V
SEP
10 MHz.
Note 15:
A minimum pulse width of 200 ns is the guaranteed minimum for a horizontal line of 15 kHz. This limit is guaranteed by design. If a lower line rate is used
then a longer clamp pulse may be required.
Note 16:
Once the spot killer has been activated, the LM1229 remains in the off state until V
CC
is cycled (reduced below 0.5V and then restored to 5V).
Note 17:
Video input = 0.7 V
and the OSD Enable is active with the OSD inputs at black. For each video input, in turn, set the specified video input at the
designated frequency and measure the video feedthrough at the video outputs.
Note 18:
In the transparency mode, the OSD background consists of video with contrast level determined by the Transparency Register. The OSD foreground is
unaffected.
Note 19:
Jitter is measured at the 31 kHz scan rate by measuring the time difference between the leading edge of HSYNC and the leading edge of the HDRIVE
output pulse.
LM1229 Test Circuit
The LM1229 RGB test circuit is shown in
Figure 2
. The video
generator should be a clean 75
source to prevent un-
wanted reflections from the terminations. The output wave-
forms should be measured with a 10X, low capacitance
probe on an oscilloscope with at least 400 MHz bandwidth.
The jumpers JP1 and JP2 determine the free running fre-
quency according to
Table 1
. The OSD inputs are shown as
analog 0.7V peak to peak. If higher level signals are avail-
able, suitable attenuation and termination should be used to
achieve the proper input level. To prevent overdriving the
input pins, the 1000 pF capacitors should be removed
(shorted) to test the digital OSD mode. Caution—Do not
apply TTL OSD input signals to the LM1229 while it is in the
analog OSD mode.
L
www.national.com
8
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