參數(shù)資料
型號: LM1229YA
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 運(yùn)動控制電子
英文描述: I2C Compatible CMOS TV RGB and Deflection Processor
中文描述: WAVEFORM GENERATION, PQFP64
封裝: PLASTIC, QFP-64
文件頁數(shù): 12/27頁
文件大小: 969K
代理商: LM1229YA
Application Information
(Continued)
Pin
No.
18
Pin Name
Schematic
Description
Horizontal
Flyback
The input is a threshold detector at
approximately 2.4V. R
H
should be large enough
to limit the combined peak current during flyback
to a few milliamperes in the zener diode in
accordance with the zener power rating.
It may be desirable to add a resistor from V
CC
or
GND to pin 18 to offset the switching point up or
down by a small amount. Be sure to start with
small offsets and work up from there.
19
22
FREQ1
FREQ2
These two pins select the frequency of the
horizontal PLL. They are tri-state and may be
hard wired for a single frequency design or
driven by a microcontroller for a multiple
frequency design. The 100
resistor is used for
ESD and arcing protection when the connections
comes from a long distance away and are
recommended even if the pins are hard wired.
The input logic states and their corresponding
scan frequencies are given in
Table 1
.
This pin provides horizontal phase
compensation, if needed, for beam current
loading. The polarity and magnitude are
selectable from the I
2
C bus. See
Table 4
, which
shows the compensation for R
EHT
= 20k. If this
correction is not needed then it can be disabled
by setting HEHT[3] to 1 and pin 20 can be left
open.
The R
EHT
resistor determines the gain of the
horizontal phase compensation, HEHT. A smaller
resistor increases the compensation and a larger
resistor decreases it. If this feature is not used,
pins 21 and 24 may be left open.
20
HEHT
21
24
REHT1
REHT2
25
FILTER2
These are the currently recommended filter
values for PLL 2. These components should be
kept as close to pins 25 and 26 as possible, and
high frequency signals should be routed away
from this filter to avoid affecting the loop.
28
FILTER1
These are the currently recommended filter
values for PLL 1. These components should be
kept as close to pins 28 and 29 as possible, and
high frequency signals should be routed away
from this filter to avoid affecting the loop.
L
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