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LT3837
14
3837fa
APPLICATIONS INFORMATION
Transformer Design
Transformer design/specication is the most critical part
of a successful application of the LT3837. The following
sections provide basic information about designing the
transformer and potential tradeoffs.
If you need help, the LTC Applications group is available to
assist in the choice and/or design of the transformer.
Turns Ratios
The design of the transformer starts with determining
duty cycle (DC). DC impacts the current and voltage stress
on the power switches, input and output capacitor RMS
currents and transformer utilization (size vs power).
The ideal turns ratio is:
N
V
DC
IDEAL
OUT
IN
=
–
1
Avoid extreme duty cycles as they, in general, increase
current stresses. A reasonable target for duty cycle is 50%
at nominal input voltage.
For instance, if we wanted a 9V to 3.3V converter at 50%
DC then:
NIDEAL ==
33
9
10 5
05
1
272
.
–.
..
In general, better performance is obtained with a lower
turns ratio. A DC of 52% yields a 1:3 ratio.
Note the use of the external feedback resistive divider
ratio to set output voltage provides the user additional
freedom in selecting a suitable transformer turns ratio.
Turns ratios that are the simple ratios of small integers;
e.g., 1:1, 2:1, 3:2 help facilitate transformer construction
and improve performance.
When building a supply with multiple outputs derived
through a multiple winding transformer, lower duty cycle
can improve cross regulation by keeping the synchronous
rectier on longer, and thus, keep secondary windings
coupled longer.
For a multiple output transformer, the turns ratio between
output windings is critical and affects the accuracy of the
voltages. The ratio between two output voltages is set with
the formula VOUT2 = VOUT1 N21 where N21 is the turns
ratio of between the two windings. Also keep the secondary
MOSFET RDS(ON) small to improve cross regulation.
Leakage Inductance
Transformer leakage inductance (on either the primary or
secondary) causes a spike after the primary side switch
turn-off. This is increasingly prominent at higher load
currents, where more stored energy is dissipated. Higher
yback voltage may break down the MOSFET switch if it
has too low a BVDSS rating.
One solution to reducing this spike is to use a snubber
circuit to suppress the voltage excursion. However, sup-
pressing the voltage extends the yback pulse width. If
the yback pulse extends beyond the enable delay time,
output voltage regulation is affected. The feedback system
has a deliberately limited input range, roughly ±50mV re-
ferred to the FB node. This rejects higher voltage leakage
spikes because once a leakage spike is several volts in
amplitude, a further increase in amplitude has little effect
on the feedback system.
So it is advisable to arrange the snubber circuit to clamp
at as high a voltage as possible, observing MOSFET
breakdown, such that leakage spike duration is as short
as possible. Application Note 19 provides a good reference
on snubber design.
As a rough guide, total leakage inductances of several per-
cent (of mutual inductance) or less may require a snubber,
but exhibit little to no regulation error due to leakage spike
behavior. Inductances from several percent up to perhaps
ten percent cause increasing regulation error.
Avoid double digit percentage leakage inductances as there
is a potential for abrupt loss of control at high load current.
This curious condition potentially occurs when the leakage
spike becomes such a large portion of the yback waveform
that the processing circuitry is fooled into thinking that the
leakage spike itself is the real yback signal!