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參數(shù)資料
| 型號： | LLT3837EFE |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 110 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 255K |
| 代理商： | LLT3837EFE |
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LT3837
23
3837fa
APPLICATIONS INFORMATION
The parasitic inductance creates an LC tank with the
MOSFET gate capacitance. In less than ideal layouts, a
series resistance of 5
Ω or more may help to dampen the
ringing at the expense of slightly slower rise and fall times
and efciency.
The LT3837 gate drives will clamp the max gate voltage
to roughly 7.5V, so you can safely use MOSFETs with max
VGS of 10V or larger.
Synchronous Gate Drive
There are several different ways to drive the synchronous
gate MOSFET. Full converter isolation requires the synchro-
nous gate drive to be isolated. This is usually accomplished
by way of a pulse transformer. Usually the pulse driver is
used to drive a buffer on the secondary as shown in the
application on the front page of this data sheet.
However, other schemes are possible. There are gate
drivers and secondary side synchronous controllers avail-
able that provide the buffer function as well as additional
features.
Capacitor Selection
In a yback converter, the input and output current ows
in pulses, placing severe demands on the input and output
lter capacitors. The input and output lter capacitors
are selected based on RMS current ratings and ripple
voltage.
Select an input capacitor with a ripple current rating
greater than:
I
P
V
DC
RMS
IN
IN MIN
MAX
=
()
–
1
Continuing the example:
I
W
V
A
RMS ==
37 5
9
152 4
52 4
397
.–
. %
.%
.
Input capacitor series resistance (ESR) and inductance
(ESL) need to be small as they affect electromagnetic
interference suppression. In some instances, high ESR can
also produce stability problems because yback converters
exhibit a negative input resistance characteristic. Refer to
Application Note 19 for more information.
The output capacitor is sized to handle the ripple current
and to ensure acceptable output voltage ripple. The output
capacitor should have an RMS current rating greater than:
II
DC
RMS
OUT
MAX
=
1–
Continuing the example::
IA
A
RMS ==
10
52 4
152 4
10 5
.%
–. %
.
This is calculated for each output in a multiple winding
application.
ESR and ESL along with bulk capacitance directly affect
the output voltage ripple. The waveforms for a typical
yback converter are illustrated in Figure 7.
OUTPUT VOLTAGE
RIPPLE WAVEFORM
SECONDARY
CURRENT
PRIMARY
CURRENT
IPRI
VCOUT
3825 F07
RINGING
DUE TO ESL
IPRI
N
VESR
Figure 7. Typical Flyback Converter Waveforms
The maximum acceptable ripple voltage (expressed as a
percentage of the output voltage) is used to establish a
starting point for the capacitor values. For the purpose
of simplicity we will choose 2% for the maximum output
ripple, divided equally between the ESR step and the
charging/discharging ΔV. This percentage ripple changes,
depending on the requirements of the application. You
can modify the following equations.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor is determined by:
ESR
VDC
I
COUT
OUT
MAX
OUT
≤
()
1
%
–
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