參數(shù)資料
型號： LLT3837EFE
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： SWITCHING CONTROLLER, 110 kHz SWITCHING FREQ-MAX, PDSO16
封裝： 4.40 MM, PLASTIC, TSSOP-16
文件頁數(shù)： 11/28頁
文件大?。?/td> 255K
代理商： LLT3837EFE
LT3837
19
3837fa
APPLICATIONS INFORMATION
Primary Gate Delay Time (PGDLY)
Primary gate delay is the programmable time from the
turn-off of the synchronous MOSFET to the turn-on of
the primary side MOSFET. Correct setting eliminates
overlap between the primary side switch and secondary
side synchronous switch(es) and the subsequent current
spike in the transformer. This spike will cause additional
component stress and a loss in regulator efciency.
The primary gate delay resistor is set with the following
equation:
Rk
tns
PGDLY
()
.
Ω=
+ 47
901
A good starting point is 27k.
Soft-Start Functions
The LT3837 contains an optional soft-start function that is
enabled by connecting an external capacitor between the
SFST pin and ground. Internal circuitry prevents the control
voltage at the VC pin from exceeding that on the SFST pin.
There is an initial pull-up circuit to quickly bring the SFST
voltage to approximately 0.8V. From there it charges to
approximately 2.8V with a 20
μA current source.
The SFST node is then discharged to 0.8V when a fault
occurs. A fault is VCC too low (undervoltage lockout),
current sense voltage greater than 200mV or the IC’s
thermal (overtemperature) shutdown is tripped. When
SFST discharges, the VC node voltage is also pulled low
to below the minimum current voltage. Once discharged,
the SFST recharges up again.
In this manner, switch currents are reduced and the stresses
in the converter are reduced during fault conditions.
The time it takes to fully charge soft-start is:
t
CV
A
ms C
F
SS
SFST
=
μ
=μ
.
(
)
14
20
70
UVLO Pin Function
The UVLO pin provides a user programming undervoltage
lockout. This is usually used to provide undervoltage
lockout based on VIN. The gate drivers are disabled when
UVLO is below the 1.24V UVLO threshold. An external
resistive divider between the input supply and ground is
used to set the turn-on voltage.
The bias current on this pin depends on the pin volt-
age and UVLO state. The change provides the user with
adjustable UVLO hysteresis. When the pin rises above
the UVLO threshold a small current is sourced out of the
pin, increasing the voltage on the pin. As the pin voltage
drops below this threshold, the current is stopped, further
dropping the voltage on UVLO. In this manner, hysteresis
is produced.
Referring to Figure 4, the voltage hysteresis at VIN is
equal to the change in bias current times RA. The design
procedure is to select the desired VIN referred voltage
hysteresis, VUVHYS. Then:
R
V
I
A
UVHYS
UVLO
=
where:
IUVLO = IUVLOL – IUVLOH is approximately 3.4μA
RB is then selected with the desired turn-on voltage:
R
V
B
A
IN ON
UVLO
=
()
–1
VIN
RA
LT3837
(3a) UV Turning ON
UVLO
IUVLO
RB
VIN
RA
LT3837
(3b) UV Turning OFF
(3c) UV Filtering
UVLO
RB
VIN
RA2
RA1
CUVLO
RB
3837 F03
IUVLO
Figure 4
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