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參數(shù)資料
| 型號： | LHF64P01 |
| 廠商： | Sharp Corporation |
| 英文描述： | 64Mbit (4Mbitx16/8Mbitx8) Page Flash Memory |
| 中文描述： | 64兆比特（4Mbitx16/8Mbitx8）頁閃存 |
| 文件頁數(shù)： | 12/45頁 |
| 文件大?。?/td> | 1041K |
| 代理商： | LHF64P01 |
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LHF64P01 10
NOTES:
1. Bus operations are defined in Table 4.
2. X=Any valid address within the device.
IA=Identifier codes address (Refer to Table 3).
QA=Query codes address. Refer to Appendix of LH28F640SP series for details.
BA=Address within the block for block erase, page buffer program or set block lock bit.
WA=Address of memory location for the Program command.
OA=Address of OTP block to be read or programmed (Refer to Figure 3).
3. The upper byte of the data bus (DQ
15
-DQ
8
) during command writes is ignored in word mode (BYTE#=V
IH
:
×
16 bit).
ID=Data to be read from identifier codes. (Refer to Table 3).
QD=Data to be read from query database.
Refer to Appendix of LH28F640SP series for details.
SRD=Data to be read from status register. Refer to Table 7 for a description of the status register bits.
WD=Data to be programmed at location WA. Data is latched on the first edge of CE
0
, CE
1
or CE
2
that disables
the device or the rising edge of WE# (whichever occurs first) during command write cycles.
N-1=N is the number of the words /bytes to be loaded into a page buffer.
OD=Data within OTP block. Data is latched on the first edge of CE
0
, CE
1
or CE
2
that disables
the device or the rising edge of WE# (whichever occurs first) during command write cycles.
CC=
STS configuration
code (Refer to Table 9).
4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock
configuration code and the data within OTP block (Refer to Table 3).
The Read Query command is available for reading CFI (Common Flash Interface) information.
5. Block erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block can be erased
or programmed when RP# is V
IH
.
6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.
7. Following the third bus cycle, write the program sequential address and data of "N" times. Finally, write the any valid
address within the block to be programmed and the confirm command (D0H).
Table 5. Command Definitions
(10)
Command
Bus
Cycles
Req
’
d
1
≥
2
≥
2
2
1
2
Notes
First Bus Cycle
Second Bus Cycle
Oper
(1)
Addr
(2)
Data
(3)
Oper
(1)
Addr
(2)
Data
(3)
Read Array
Read Identifier Codes/OTP
Read Query
Read Status Register
Clear Status Register
Block Erase
Program
Write
Write
Write
Write
Write
Write
X
X
X
X
X
BA
FFH
90H
98H
70H
50H
20H
40H or
10H
E8H
4
4
Read
Read
Read
IA or OA
QA
X
ID or OD
QD
SRD
5
Write
BA
D0H
2
5,6
Write
X
Write
WA
WD
Page Buffer Program
Block Erase and (Page Buffer)
Program Suspend
Block Erase and (Page Buffer)
Program Resume
STS Configuration
Set Block Lock Bit
Clear Block Lock Bits
OTP Program
≥
4
5,7
Write
BA
Write
BA
N-1
1
8
Write
X
B0H
1
8
Write
X
D0H
2
2
2
2
Write
Write
Write
Write
X
X
X
X
B8H
60H
60H
C0H
Write
Write
Write
Write
X
BA
X
OA
CC
01H
D0H
OD
9
Rev. 0.06
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