參數(shù)資料
型號: LH75411N0Q100C0
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: System-on-Chip
封裝: LH75401N0Q100C0<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;LH75411N0Q100C0<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1
文件頁數(shù): 54/63頁
文件大?。?/td> 665K
代理商: LH75411N0Q100C0
LH75401/LH75411
System-on-Chip
54
Rev. 01
16 July 2007
Preliminary data sheet
NXP Semiconductors
Figure 19. AD-TFT, HR-TFT Horizontal Timing Diagram
Figure 20. AD-TFT, HR-TFT Vertical Timing Diagram
1 AD-TFT or HR-TFT HORIZONTAL LINE
AD-TFT and HR-TFT SIGNALS ARE TFT SIGNALS, RE-TIMED
Timing0:HSW
Timing0:HSW +
Timing0: HBP
PIXEL DATA
1 LCDDCLK
002 003 004 005 006
318
317
319 320
001
1 LCDDCLK
Timing1:LPDEL
Timing1:CLSDEL
Timing1:REVDEL
Timing2:CLSDEL2
002 003 004 005 006 007 008
320
001
*
CLCDCLK
(INTERNAL)
APBPeriphClkCtrl1:LCD
ClkPrescale:LCDPS
(SHOWN FOR REFERENCE)
LCDLP
(HORIZONTAL
SYNCHRONIZATION
PULSE)
I
A
O
A
LCDDCLK
(PANEL CLOCK)
Timing2:PCD
Timing2:BCD
Timing2:IPC
Timing2:CPL
LCDVD[11:0]
LCDDCLK
(DELAYED FOR
AD-TFT, HR-TFT)
LCDVD[11:0]
(DELAYED FOR
AD-TFT, HR-TFT)
LCDSPL
(AD-TFT, HR-TFT
START PULSE LEFT)
LCDLP
(HORIZONTAL
SYNCHRONIZATION
PULSE)
LCDCLS
LCDPS
LCDREV
LCDEN
(DATA ENABLE)
LH754xx-80
NOTE:
*
Source is RCPC.
LCDSPS
(VERTICAL
SYNCHRONIZATION)
LCDLP
(HORIZONTAL
SYNCHRONIZATION
PULSE)
LCDVD[11:0]
(LCD VIDEO DATA)
NOTE
: LCDDCLK can range from 4.5 MHz to 6.8 MHz.
LH754xx-81
Timing1:VSW
1.5 μs - 4 μs
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LH75411N0Q100C0,55 功能描述:ARM微控制器 - MCU LCD,EXT BUS,ADC,QFP144 RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT
LH75411N0Q100C0,551 制造商:NXP Semiconductors 功能描述:
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