System-on-Chip
LH75401/LH75411
Preliminary data sheet
Rev. 01
—
16 July 2007
27
NXP Semiconductors
Color LCD Controller (CLCDC)
The CLCDC is an AMBA master-slave module that
connects to the AHB. It translates pixel-coded data into
the required formats and timings to drive single/dual
monochrome and color LCD panels. Packets of pixel-
coded data are fed, via the AHB interface, to two inde-
pendently programmable, 32-bit-wide DMA FIFOs.
Each FIFO is 16 words deep by 32 bits wide.
The CLCDC generates a single combined interrupt
to the Vectored Interrupt Controller (VIC) when an
interrupt condition becomes true for upper/lower panel
DMA FIFO underflow, base address update significa-
tion, vertical compare, or bus error.
NOTE:
LH75401 and LH75411 microcontrollers support full-color
operation.
CLCDC FEATURES
STN, Color STN, TFT, HR-TFT, and AD-TFT
– Fully Programmable Timing Controls
– Advanced LCD Interface for displays with a low
level of integration, such as HR-TFT and AD-TFT
Programmable Resolution
– Up to VGA (640 × 480 DPI), 12-bit Direct Mode
Color
– Up to SVGA (800 × 600 DPI), 8-bit Direct/Palet-
tized Color
– Up to XGA (1,024 × 768 DPI), 4-bit Direct Color/
Grayscale
– Direct or Palettized Colors
Single and Dual Panels
Supports Sharp and non-Sharp Panels
CLCDC Outputs Available as General Purpose
Inputs/Outputs (GPIOs) if LCDC is Not Needed
Additional Features
– Fully programmable horizontal and vertical timing
for different display panels
– 256-entry, 16-bit palette RAM physically arranged
as a 128 × 32-bit RAM
– AC bias signal for STN panels and a data-enable
signal for TFT panels.
Programmable Panel-related Parameters
– STN mono/color or TFT display
– Bits-per-pixel
– STN 4- or 8-bit Interface Mode
– STN Dual or Single Panel Mode
– AC panel bias
– Panel clock frequency
– Number of panel clocks per line
– Signal polarity, active HIGH or LOW
– Little Endian data format
– Interrupt-generation event.
ADVANCED LCD INTERFACE
The Advanced LCD Interface (ALI) allows for direct
connection to ultra-thin panels that do not include a tim-
ing ASIC. It converts TFT signals from the Color LCD
controller to provide the proper signals, timing and levels
for direct connection to a panel’s Row and Column driv-
ers for AD-TFT, HR-TFT, or any technology of panel that
allows for a connection of this type. The ALI also pro-
vides a bypass mode that allows interfacing to the built-
in timing ASIC in standard TFT and STN panels.
NOTES:
1. The Advanced LCD Interface pertains to the LH75401 and
LH75411 microcontrollers.
2. VGA and XGA modes require 66 MHz core speed.
Universal Asynchronous
Receiver Transmitters (UARTs)
The LH75401/LH75411 microcontrollers incorporate
three UARTs, designated UART0, UART1, and UART2.
UART 0 AND 1 FEATURES
Similar functionality to the industry-standard 16C550
Supported baud rates up to 921,600 baud (given an
external crystal frequency of 14.756 MHz)
Supported character formats:
– Data bits per character: 5, 6, 7, or 8
– Parity generation and detection: Even, odd, stick,
or none
– Stop bit generation: 1 or 2
Full-duplex operation
Separate transmit and receive FIFOs, with:
– Programmable depth (1 to 16)
– Programmable-service ‘trigger levels’ (1/8, 1/4,
1/2, 3/4, and 7/8)
– Overrun protection.
Programmable baud-rate generator that:
– Enables the UART input clock to be divided by 16
to 65,535 × 16
– Generates an internal clock common to both
transmit and receive portions of the UART.
DMA support
Support for generating and detecting breaks during
UART transactions
Loopback testing.