參數(shù)資料
型號: LH75411N0Q100C0
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: System-on-Chip
封裝: LH75401N0Q100C0<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;LH75411N0Q100C0<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1
文件頁數(shù): 40/63頁
文件大小: 665K
代理商: LH75411N0Q100C0
LH75401/LH75411
System-on-Chip
40
Rev. 01
16 July 2007
Preliminary data sheet
NXP Semiconductors
AC Characteristics
All signal transitions are measured from the 50 %
point of the signal.
NOTE:
The values in Table 24 represent the timing with no internal arbitration
delay and 1 wait state memory access. This is the worst case (fastest) timing.
Table 24. Memory Interface Signals
SIGNAL
I/O LOAD PARAMETER
MINIMUM
MAXIMUM
COMMENTS
D[15:0]
Out 50 pF
tOVD
tHCLK + 8 ns
Data output valid following address valid
D[15:0]
Out 50 pF
tOHD
3 × tHCLK – 6 ns
Data output invalid following address valid
D[15:0]
In
tIDD
2 tHCLK – 18 ns Data input valid following address valid
2 × tHCLK – 18 ns
+ (nWAIT –1)
× tHCLK
Data Input Valid, following
Address Valid (nWAIT states)
nCS3 - nCS0
Out 30 pF
tOVCS
tHCLK + 6 ns
nCS output valid following address valid
nCS3 -nCS0
Out 30 pF
tOHCS
3 × tHCLK – 6 ns
nCS output invalid following address valid
nOE
Out 30 pF
tOVOE
tHCLK + 10 ns
nOE output valid following address valid
nOE
Out 30 pF
tOHOE
3 × tHCLK – 6 ns
nOE output invalid following address valid
nBLE1 - nBLE0 Out 30 pF
tOVBE
tHCLK + 10 ns
nBLE output valid following address valid
nBLE1 - nBLE0 Out 30 pF
tOHBER
3 × tHCLK – 6 ns
nBLE output invalid following address
valid, read cycle
nBLE1 - nBLE0 Out 30 pF
tOHBEW
2 × tHCLK – 6 ns
nBLE output invalid following address
valid, write cycle
nWE
Out 30 pF
tOVWE
tHCLK + 10 ns
nWE output valid following address valid
nWE
Out 30 pF
tOHWE
2 × tHCLK – 6 ns 2 tHCLK – 2.2 ns nWE output invalid following address valid
nWAIT
In
tIVWAIT
2 tHCLK – 18 ns nWAIT input valid following address valid
Table 25. Synchronous Serial Port
SIGNAL
I/O
LOAD
PARAMETER
MIN.
MAX.
COMMENT
SSPFRM
SSPTX
SSPRX
Out
Out
In
50 pF
50 pF
tOVSSPFRM
tOVSSPTX
tISSPRX
14 ns
12 ns
SSPFRM output valid, referenced to SSPCLK
SSPTX output valid, referenced to SSPCLK
SSPRX input valid, referenced to SSPCLK
22 ns
Table 26. Power-up Stabilization
PARAMETER
DESCRIPTION
TYP.
MAX.
UNIT
tLREG
Linear regulator stabilization time after power-up
200
μ
s
tOSC32
Oscillator stabilization time after Power Up (VDDC = VDDCMIN)
550
ms
tOSC14
Oscillator stabilization time after Power Up (VDDC = VDDCMIN)
2.5
ms
tRSTOV
nPOR LOW to nPOR valid (once sampled LOW)
3.5
HCLK
μ
s
tPORH
nPOR hold extend to allow PLL to lock once XTAL is stable
10
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