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| 型號(hào)： | LFXP20E-5FN484C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 中文描述： | FPGA, 2464 CLBS, PBGA484 |
| 封裝： | 23 X 23 MM, LEAD FREE, FPBGA-484 |
| 文件頁(yè)數(shù)： | 89/130頁(yè) |
| 文件大?。?/td> | 1312K |
| 代理商： | LFXP20E-5FN484C |
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4-2
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
Test and Programming (Dedicated pins. Pull-up is enabled on input pins during configuration.)
TMS
I
Test Mode Select input, used to control the 1149.1 state machine.
TCK
I
Test Clock input pin, used to clock the 1149.1 state machine.
TDI
I
Test Data in pin, used to load data into device using 1149.1 state machine.
After power-up, this TAP port can be activated for configuration by sending
appropriate command. (Note: once a configuration port is selected it is
locked. Another configuration port cannot be selected until the power-up
sequence).
TDO
O
Output pin -Test Data out pin used to shift data out of device using 1149.1.
VCCJ
—VCCJ - The power supply pin for JTAG Test Access Port.
Configuration Pads (used during sysCONFIG)
CFG[1:0]
I
Mode pins used to specify configuration modes values latched on rising edge
of INITN. During configuration, a pull-up is enabled.
INITN
I/O
Open Drain pin - Indicates the FPGA is ready to be configured. During con-
figuration, a pull-up is enabled. If CFG1 and CFG0 are high (SDM) then this
pin is pulled low.
PROGRAMN
I
Initiates configuration sequence when asserted low. This pin always has an
active pull-up.
DONE
I/O
Open Drain pin - Indicates that the configuration sequence is complete, and
the startup sequence is in progress.
CCLK
I/O
Configuration Clock for configuring an FPGA in sysCONFIG mode.
BUSY
I/O
Generally not used. After configuration it is a user-programmable I/O pin.
CSN
I
sysCONFIG chip select (Active low). During configuration, a pull-up is
enabled. After configuration it is user a programmable I/O pin.
CS1N
I
sysCONFIG chip select (Active Low). During configuration, a pull-up is
enabled. After configuration it is user programmable I/O pin
WRITEN
I
Write Data on Parallel port (Active low). After configuration it is a user pro-
grammable I/O pin
D[7:0]
I/O
sysCONFIG Port Data I/O. After configuration these are user programmable
I/O pins.
DOUT, CSON
O
Output for serial configuration data (rising edge of CCLK) when using sys-
CONFIG port. After configuration, it is a user-programmable I/O pin.
DI
I
Input for serial configuration data (clocked with CCLK) when using sysCON-
FIG port. During configuration, a pull-up is enabled. After configuration it is a
user-programmable I/O pin.
SLEEPN
2
I
Sleep Mode pin - Active low sleep pin. When this pin is held high, the device
operates normally. When driven low, the device moves into Sleep Mode
after a specified time.This pin has a weak internal pull-up, but when not used
an external pull-up to VCC is recommended.
TOE
3
I
Test Output Enable tri-states all I/O pins when driven low. This pin has a
weak internal pull-up, but when not used an external pull-up to VCC is recom-
mended.
1. Applies to LFXP10, LFXP15 and LFXP20 only.
2. Applies to LFXP “C” devices only.
3. Applies to LFXP “E” devices only.
Signal Descriptions (Cont.)
Signal Name
I/O
Descriptions
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| LFXP217E5CF484C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet |
| LFXP217E5CF484I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet |
| LFXP217E5CF672C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet |
| LFXP217E5CF672I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet |
| LFXP217E5CFN484C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet |
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