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參數(shù)資料
| 型號(hào)： | LFXP20E-5FN484C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 中文描述： | FPGA, 2464 CLBS, PBGA484 |
| 封裝： | 23 X 23 MM, LEAD FREE, FPBGA-484 |
| 文件頁(yè)數(shù)： | 36/130頁(yè) |
| 文件大小： | 1312K |
| 代理商： | LFXP20E-5FN484C |
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7-2
Revision History
Lattice Semiconductor
LatticeXP Family Data Sheet
September 2005
(cont.)
03.0
(cont.)
DC and Switching
Characteristics (cont.)
Updated Typical Building Block Function Performance timing numbers.
Updated External Switching Characteristics timing numbers.
Updated Internal Timing Parameters.
Updated LatticeXP Family timing adders.
Updated LatticeXP "C" Sleep Mode timing numbers.
Updated JTAG Port Timing numbers.
Pinout Information
Added clarification to SLEEPN and TOE description.
Clarification of dedicated LVDS outputs.
Supplemental
Information
Updated list of technical notes.
September 2005
03.1
Pinout Information
Power Supply and NC Connections table corrected VCCP1 pin number
for 208 PQFP.
December 2005
04.0
Introduction
Moved data sheet from Advance to Final.
Architecture
Added clarification to Typical I/O Behavior During Power-up section.
DC and Switching
Characteristics
Added clarification to Recommended Operating Conditions.
Updated timing numbers.
Pinout Information
Updated Signal Descriptions table.
Added clarification to Differential I/O Per Bank.
Updated Differential dedicated LVDS output support.
Ordering Information
Added 208 PQFP lead-free package and ordering part numbers.
February 2006
04.1
Pinout Information
Corrected description of Signal Names VREF1(x) and VREF2(x).
March 2006
04.2
DC and Switching
Characteristics
Corrected condition for IIL and IIH.
March 2006
04.3
DC and Switching
Characteristics
Added clarification to Recommended Operating Conditions for
VCCAUX.
April 2006
04.4
Pinout Information
Removed Bank designator "5" from SLEEPN/TOE ball function.
May 2006
04.5
DC and Switching
Characteristics
Added footnote 2 regarding threshold level for PROGRAMN to sysCON-
FIG Port Timing Specifications table.
June 2006
04.6
DC and Switching
Characteristics
Corrected LVDS25E Output Termination Example.
August 2006
04.7
Architecture
Added clarification to Typical I/O Behavior During Power-Up section.
Added clarification to Left and Right sysIO Buffer Pair section.
DC and Switching
Characteristics
Changes to LVDS25E Output Termination Example diagram.
December 2006
04.8
Architecture
EBR Asynchronous Reset section added.
February 2007
04.9
Architecture
Updated EBR Asynchronous Reset section.
July 2007
05.0
Introduction
Updated LatticeXP Family Selection Guide table.
Architecture
Updated Typical I/O Behavior During Power-up text section.
DC and Switching
Characteristics
Updated sysIO Single-Ended DC Electrical Characteristics table. Split
out LVCMOS 1.2 by supply voltage.
November 2007
05.1
DC and Switching
Characteristics
Added JTAG Port Timing Waveforms diagram.
Pinout Information
Added Thermal Management text section.
Supplemental
Information
Updated title list.
Date
Version
Section
Change Summary
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| LFXP217E5CF484C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet |
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| LFXP217E5CF672C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet |
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| LFXP217E5CFN484C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet |
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