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參數(shù)資料
| 型號： | L9942 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Super Smart Motor Bridge Driver(電機(jī)橋驅(qū)動器) |
| 中文描述： | 超級智能電機(jī)橋式驅(qū)動器（電機(jī)橋驅(qū)動器） |
| 文件頁數(shù)： | 12/21頁 |
| 文件大?。?/td> | 160K |
| 代理商： | L9942 |
STOP
XTAL
C1
C2OSCOUT
OSCIN
MAIN
OSC
CPU
÷
12
÷
4
WATCH
DOG
MUX2
0
1
MUX1
0
1
OSCR
X
X
TEST
READY
FC2
FC1
FC0
COUNT
RESET
CAN CONTROLLER
MAINCLK
4 .. 8MHz
32kHz
SBCLK
INT#3
INT#4
CONTACT MON.
CLOCK
INPUT
TIMER1
MUX3
0
1
COUNT
LOGIC
PA2/TIMER
EXT. TEST INPUT
3
GATE
RC
OSC
STOP
MSB
LSB
Figure 6. Systemclockingscheme.
The CPU and digital logic is supplied with a clocksignal MAINCLK from main oscillator usingan external
xtal or ceramic resonator. Two external capacitors C1 and C2 of 12 - 22pF each (according to the rec-
ommendationof the resonatorsupplier) have to be connectedto the oscillator pins. OSCIN is the input,
OSCOUT is the output of the main oscillator. Also an external clock signal can be applied to OSCIN to
clock the device.Maximum frequencyof the mainoscillatoris 8MHz.
For standby operation the main oscillator is switched off by executionof a STOP instruction of the appli-
cation software.After this instructionthe CPU is in stop mode:
- no operation is performed
- all registersand memory cells keep their content
- voltageregulator is switched to standbymode
- currentconsumptionis minimized
- contactmonitors, TIMER1,watchdog are suppliedwith standby clockSBCLK
This state can be left only by interrupts (contact monitors, I/O, CAN-controller, timer) or by reset (exter-
nal, voltageregulator,watchdog).
In order to keep some basic functionsin standby mode there is a separate low power RC oscillator. The
oscillator frequency of about 32kHz is generated using internal components only. This standby oscillator
operates permanently and cannot be stopped. It’s output signal SBCLK supplies the contact monitor cir-
cuitry as well as TIMER1 and watchdog (in STOP mode only). This configuration allows periodic CPU
wake up from STOP mode by timer interrupts as well as watchdog operationalso in STOP mode. There-
forein caseof failureof the wake up mechanismthe STOP mode is left by a watchdoggeneratedreset.
MICROCONTROLLER SECTION
(continued)
L9942
12/21
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