參數(shù)資料
型號: KSZ8893FQL
廠商: Micrel Inc
文件頁數(shù): 95/117頁
文件大?。?/td> 0K
描述: IC SWITCH FAST ETH 3PORT 128PQFP
標(biāo)準(zhǔn)包裝: 66
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: MII,RMII,SNI
電源電壓: 3.1 V ~ 3.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
配用: 576-1603-ND - EVAL KIT EXPERIMENTAL KSZ8893MQL
其它名稱: 576-1565
Micrel, Inc.
KSZ8893FQL
October 2007
79
M9999-101607-1.3
TS-1000 Media Converter Registers
Register 64 (0x40): PHY Address
Bit
Name
R/W
Description
Default
7-5
Number of Indication
OAM frame(s)
R/W
Set the number of Indication OAM frame(s) to be transmitted
for a single OAM status change. This setting is applicable to
only the following three OAM frames: Indicate Center MC
Condition, Indicate Terminal MC Condition, and Loop Mode
Stop Indication.
000 : send 1 OAM frame
001 : send 2 OAM frames
010 : send 3 OAM frames
011 : send 4 OAM frames
100 : send 5 OAM frames
101 : N/A
110 : N/A
111 : N/A
000
4
Addr4
R/W
0
3
Addr3
R/W
0
2
Addr2
R/W
0
1
Addr1
R/W
0
Addr0
R/W
These 5-bits set the PHY addresses for port 1 and port 2.
00000 : N/A
00001 : Port 1 PHY address is 0x1
00010 : Port 1 PHY address is 0x2
11101 : Port 1 PHY address is 0x29
11110 : N/A
11111 : N/A
Port 2 PHY address = (Port 1 PHY address) + 1
Note:
In Center side MC mode (pins MCHS,MCCS] = [0,1]), a write
to these bits with port 1’s PHY address is required to enable
port 1 and start the Center side MC.
1
Register 65 (0x41): Center Side Status
Bit
Name
R/W
Description
Default
7
BUSY
RO
1 = Indicate MC loop back mode in progress, or receive reply
frame/timeout is pending
0 = Exclude the above situations
0
6
Vendor mode
R/W
1 = Non special vendor mode
0 = Special vendor mode (compare My & LNK Partner Vendor
Info = 0x009099h)
0
5-3
Reserved
RO
Reserved
Do not change the default values.
000
2
Option b
R/W
1 = Clear status bits S6 to S10 to zero on Terminal MC side
0 = Normal operation – supporting option b
0
1
Option a
R/W
1 = Disable “Indicate Center MC Condition” frame
0 = Enable “Indicate Center MC condition” frame
0
Request
RO
1 = indicate change of status/value in registers # 0x50h,
0x51h, 0x58h, 0x59h, 0x5Dh, 0x5Eh, 0x5Fh. This bit is self-
cleared after a read.
0 = exclude the above situations
0
Note
: This register is managed by the Center side.
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