參數(shù)資料
型號(hào): KSZ8893FQL
廠商: Micrel Inc
文件頁數(shù): 39/117頁
文件大?。?/td> 0K
描述: IC SWITCH FAST ETH 3PORT 128PQFP
標(biāo)準(zhǔn)包裝: 66
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: MII,RMII,SNI
電源電壓: 3.1 V ~ 3.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
配用: 576-1603-ND - EVAL KIT EXPERIMENTAL KSZ8893MQL
其它名稱: 576-1565
Micrel, Inc.
KSZ8893FQL
October 2007
28
M9999-101607-1.3
Strapping Pin (#)
MIIM Register #, Bit[#]
Port Register #, Bit[#]
100Base-SX Settings
Auto-Negotiation (disable only)
P1ANEN (30)
Reg. 0, Bit[12]
Reg. 28, Bit[7]
Speed (100Mbps only)
P1SPD (31)
Reg. 0, Bit[13]
Reg. 28, Bit[6]
Duplex (half or full)
P1DPX (32)
Reg. 0, Bit[8]
Reg. 28, Bit[5]
Forced Flow Control (option)
P1FFC (33)
---
Reg. 18, Bit[4]
Table 4. 100Base-SX Configuration
Functional Overview: Physical Layer Transceiver
100Base-TX Transmit
The 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial
bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized
data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is
set by an external 1% 3.01K
resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10Base-T output is also incorporated into the 100Base-TX
transmitter.
100Base-TX Receive
The 100Base-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted
pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for
optimization. This is an ongoing process and self-adjusts against environmental changes such as temperature
variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used
to compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion
circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B
decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
PLL Clock Synthesizer
The KSZ8893FQL generates 125MHz, 31.25MHz, 25MHz, and 10MHz clocks for system timing. Internal clocks are
generated from an external 25MHz crystal or oscillator. In RMII mode, these internal clocks are generated from an
external 50MHz oscillator or system clock.
Scrambler/De-scrambler (100Base-TX Only)
The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference
(EMI) and baseline wander. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift
register (LFSR). The scrambler generates a 2047-bit non-repetitive sequence, and the receiver then de-scrambles the
incoming data stream using the same sequence as at the transmitter.
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