參數(shù)資料
型號(hào)： KSZ8864RMN-EVAL
廠商： Micrel Inc
文件頁(yè)數(shù)： 56/111頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR KSZ8864RMN
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng)控制器（PHY 和 MAC）
嵌入式： 否
已用 IC / 零件： KSZ8864RMN
已供物品： 板
相關(guān)產(chǎn)品： 576-3787-ND - IC ETHERNET SW 4PORT 64QFN
其它名稱： 576-3869
1997 Microchip Technology Inc.
DS30444E - page 49
PIC16C9XX
7.3.1
SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software con-
trol, i.e., it can be changed “on the y” during program
execution.
Note:
To avoid an unintended device RESET, the
following instruction sequence (shown in
Example 7-1) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This precaution must
be followed even if the WDT is disabled.
EXAMPLE 7-1:
CHANGING PRESCALER (TIMER0
→WDT)
To change prescaler from the WDT to the Timer0 mod-
ule use the precaution shown in Example 7-2.
EXAMPLE 7-2:
CHANGING PRESCALER (WDT
→TIMER0)
CLRWDT
;Clear WDT and prescaler
BSF
STATUS, RP0 ;Select Bank1
MOVLW
b'xxxx0xxx' ;Select TMR0, new prescale value and
MOVWF
OPTION_REG
;clock source
BCF
STATUS, RP0 ;Select Bank0
TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER0
1)
BSF
STATUS, RP0
;Select Bank1
Lines 2 and 3 do NOT have to
be included if the nal desired
prescale value is other than 1:1.
If 1:1 is nal desired value, then
a temporary prescale value is
set in lines 2 and 3 and the nal
prescale value will be set in lines
10 and 11.
2)
MOVLW
b'xx0x0xxx'
;Select clock source and prescale value of
3)
MOVWF
OPTION_REG
;other than 1:1
4)
BCF
STATUS, RP0
;Select Bank0
5)
CLRF
TMR0
;Clear TMR0 and prescaler
6)
BSF
STATUS, RP1
;Select Bank1
7)
MOVLW
b'xxxx1xxx'
;Select WDT, do not change prescale value
8)
MOVWF
OPTION_REG
;
9)
CLRWDT
;Clears WDT and prescaler
10) MOVLW
b'xxxx1xxx'
;Select new prescale value and WDT
11) MOVWF
OPTION_REG
;
12) BCF
STATUS, RP0
;Select Bank0
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
01h, 101h
TMR0
Timer0 module’s register
xxxx xxxx
uuuu uuuu
0Bh, 8Bh,
10Bh, 18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
81h, 181h
OPTION RBPU INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
85h
TRISA
—
PORTA Data Direction Control Register
--11 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
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