參數(shù)資料
型號： KSZ8864RMN-EVAL
廠商： Micrel Inc
文件頁數(shù)： 100/111頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR KSZ8864RMN
標準包裝： 1
主要目的： 接口，以太網(wǎng)控制器（PHY 和 MAC）
嵌入式： 否
已用 IC / 零件： KSZ8864RMN
已供物品： 板
相關產(chǎn)品： 576-3787-ND - IC ETHERNET SW 4PORT 64QFN
其它名稱： 576-3869
1997 Microchip Technology Inc.
DS30444E - page 89
PIC16C9XX
13.0
LCD MODULE
The LCD module generates the timing control to drive
a static or multiplexed LCD panel, with support for up to
32 segments multiplexed with up to 4 commons. It also
provides control of the LCD pixel data.
The interface to the module consists of 3 control regis-
ters (LCDCON, LCDSE, and LCDPS) used to dene
the timing requirements of the LCD panel and up to 16
LCD data registers (LCD00-LCD15) that represent the
array of the pixel data. In normal operation, the control
registers are congured to match the LCD panel being
used. Primarily, the initialization information consists of
selecting the number of commons required by the LCD
panel, and then specifying the LCD Frame clock rate to
be used by the panel.
Once the module is initialized for the LCD panel, the
individual bits of the LCD data registers are cleared/set
to represent a clear/dark pixel respectively.
Once
the
module
is
congured,
the
LCDEN
(LCDCON<7>) bit is used to enable or disable the LCD
module. The LCD panel can also operate during sleep
by clearing the SLPEN (LCDCON<6>) bit.
Figure 13-4 through Figure 13-7 provides waveforms
for Static, 1/2, 1/3, and 1/4 MUX drives.
FIGURE 13-1: LCDCON REGISTER (ADDRESS 10Fh)
R/W-0
U-0
R/W-0
LCDEN
SLPEN
—
VGEN
CS1
CS0
LMUX1
LMUX0
R =Readable bit
W =Writable bit
U =Unimplemented bit,
Read as ‘0’
-n =Value at POR reset
bit7
bit0
bit 7:
LCDEN: Module drive enable bit
1 = LCD drive enabled
0 = LCD drive disabled
bit 6:
SLPEN: LCD display sleep enable
1 = LCD module will stop operating during SLEEP
0 = LCD module will continue to display during SLEEP
bit 5:
Unimplemented: Read as '0'
bit 4:
VGEN: Voltage Generator Enable
1 = Internal LCD Voltage Generator Enabled, (powered-up)
0 = Internal LCD Voltage Generator powered-down, voltage is expected to be provided externally
bit 3-2: CS1:CS0: Clock Source Select bits
00 = Fosc/256
01 = T1CKI (Timer1)
1x = Internal RC oscillator
bit 1-0:
LMUX1:LMUX0: Common Selection bits
Species the number of commons and the bias method
LMUX1:LMUX0
MULTIPLEX
BIAS
Max # of Segments
00
01
10
11
Static (COM0)
1/2
(COM0, 1)
1/3
(COM0, 1, 2)
1/4
(COM0, 1, 2, 3)
Static
1/3
32
31
30
29
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