參數(shù)資料
型號(hào)： KS8993MI
廠商： Micrel Inc
文件頁(yè)數(shù)： 69/85頁(yè)
文件大?。?/td> 0K
描述： IC SWITCH 10/100 3PORT 128PQFP
標(biāo)準(zhǔn)包裝： 66
系列： *
類型： *
應(yīng)用： *
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 散裝
配用： 576-1013-ND - BOARD EVAL EXPERIMENT KS8993M
其它名稱： 576-1014
Micrel, Inc.
KS8993M/ML/MI
April 2005
71
M9999-041205
Offset
Counter Name
Description
0x1B
TxDeferred
Tx packets by a port for which the 1st Tx attempt is delayed due to the busy
medium
0x1C
TxTotalCollision
Tx total collision, half duplex only
0x1D
TxExcessiveCollision
A count of frames for which Tx fails due to excessive collisions
0x1E
TxSingleCollision
Successfully Tx frames on a port for which Tx is inhibited by exactly one collision
0x1F
TxMultipleCollision
Successfully Tx frames on a port for which Tx is inhibited by more than one collision
Table 17. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets
Bit
Name
R/W
Description
Default
30-16
Reserved
N/A
Reserved
N/A
15-0
Counter values
RO
Counter value
0
Table 18. Format of “All Port Dropped Packet” MIB Counters
“All Port Dropped Packet” MIB counters are read using indirect memory access. The address offsets for these
counters are shown in the following table:
Offset
Counter Name
Description
0x100
Port1 TX Drop Packets
TX packets dropped due to lack of resources
0x101
Port2 TX Drop Packets
TX packets dropped due to lack of resources
0x102
Port3 TX Drop Packets
TX packets dropped due to lack of resources
0x103
Port1 RX Drop Packets
RX packets dropped due to lack of resources
0x104
Port2 RX Drop Packets
RX packets dropped due to lack of resources
0x105
Port3 RX Drop Packets
RX packets dropped due to lack of resources
Table 19. “All Port Dropped Packet” MIB Counters Indirect Memory Offsets
Examples:
1. MIB Counter Read (Read port 1 “Rx64Octets” Counter)
Write to reg. 110 with 0x1c (read MIB counters selected)
Write to reg. 111 with 0x0e (trigger the read operation)
Then
Read reg. 117 (counter value 30-24) // If bit 30 = 0, restart (reread) from this register
Read reg. 118 (counter value 23-16)
Read reg. 119 (counter value 15-8)
Read reg. 120 (counter value 7-0)
2. MIB Counter Read (Read Port 2 “Rx64Octets” Counter)
Write to reg. 110 with 0x1c (read MIB counter selected)
Write to reg. 111 with 0x2e (trigger the read operation)
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