- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369586 > KP80524NY450128 Microprocessor PDF資料下載
參數(shù)資料
| 型號： | KP80524NY450128 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 6/81頁 |
| 文件大?。?/td> | 598K |
| 代理商： | KP80524NY450128 |
第1頁第2頁第3頁第4頁第5頁當前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁
Mobile Intel
Celeron Processor (0.18μ) in BGA2 and Micro-PGA2 Packages
Datasheet
Order Number#249563-001
6
Figures
Figure 1. Signal Groups of a Mobile Intel Celeron Processor/440MX Chipset - Based
System
....................................................................................................................9
Figure 2. Clock Control States
......................................................................................14
Figure 3. Vcc Ramp Rate Requirement
.........................................................................19
Figure 4. PLL RLC Filter
...............................................................................................22
Figure 5. PICCLK/TCK Clock Timing Waveform
............................................................34
Figure 6. BCLK Timing Waveform
.................................................................................34
Figure 7. Valid Delay Timings
.......................................................................................35
Figure 8. Setup and Hold Timings
.................................................................................35
Figure 9. Cold/Warm Reset and Configuration Timings
.................................................36
Figure 10. Power-on Reset Timings
..............................................................................36
Figure 11. Test Timings (Boundary Scan)
.....................................................................37
Figure 12. Test Reset Timings
......................................................................................37
Figure 13. Quick Start/Deep Sleep Timing
....................................................................38
Figure 14. Stop Grant/Sleep/Deep Sleep Timing
...........................................................39
Figure 15. BCLK/PICCLK Generic Clock Waveform
......................................................41
Figure 16. Low to High, GTL+ Receiver Ringback Tolerance
.........................................42
Figure 17. High to Low, GTL+ Receiver Ringback Tolerance
.........................................43
Figure 18. Maximum Acceptable Overshoot/Undershoot Waveform
..............................44
Figure 19. Surface-mount BGA2 Package - Top and Side View
.....................................47
Figure 20. Surface-mount BGA2 Package - Bottom View
..............................................48
Figure 21. Socketable Micro-PGA2 Package - Top and Side View
................................50
Figure 22. Socketable Micro-PGA2 Package - Bottom View
..........................................51
Figure 23. Pin/Ball Map - Top View
...............................................................................52
Figure 24. PWRGOOD Relationship at Power On
.........................................................71
Figure 25. PLL Filter Specifications
...............................................................................79
相關PDF資料 |
PDF描述 |
|---|---|
| RH8053GC017512 | Microprocessor |
| RH8053GC021512 | Microprocessor |
| RH8053GC025512 | Microprocessor |
| RH8053GC029512 | Microprocessor |
| RH8053GC033512 | Microprocessor |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| KP80526NY700128 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Intel 功能描述: |
| KP80S 3601F200 | 制造商:STKE 功能描述: |
| KP80S 3602F100 | 制造商:STKE 功能描述: |
| KP80S1801F100 | 制造商:STK ELECTRONICS 功能描述: |
| KP80S2202J600 | 制造商:n/a 功能描述:AF322X600 5% |
發(fā)布緊急采購，3分鐘左右您將得到回復。