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參數(shù)資料
| 型號： | K7A403601A-QC140 |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 CACHE SRAM, 4 ns, PQFP100 |
| 封裝： | 20 X 14 MM, TQFP-100 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 401K |
| 代理商： | K7A403601A-QC140 |
K7A403601A
128Kx36 Synchronous SRAM
- 5 -
Rev 1.0
May 2000
SYNCHRONOUS TRUTH TABLE
Notes : 1. X means "Don
′t Care".
2. The rising edge of clock is symbolized by
↑.
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
CS1
CS2
ADSP ADSC
ADV
WRITE
CLK
ADDRESS ACCESSED
OPERATION
H
X
L
X
↑
N/A
Not Selected
L
X
L
X
↑
N/A
Not Selected
L
X
H
L
X
↑
N/A
Not Selected
L
X
L
X
↑
N/A
Not Selected
L
X
H
X
L
X
↑
N/A
Not Selected
L
H
L
X
↑
External Address
Begin Burst Read Cycle
L
H
L
H
L
X
L
↑
External Address
Begin Burst Write Cycle
L
H
L
H
L
X
H
↑
External Address
Begin Burst Read Cycle
X
H
L
H
↑
Next Address
Continue Burst Read Cycle
H
X
H
L
H
↑
Next Address
Continue Burst Read Cycle
X
H
L
↑
Next Address
Continue Burst Write Cycle
H
X
H
L
↑
Next Address
Continue Burst Write Cycle
X
H
↑
Current Address
Suspend Burst Read Cycle
H
X
H
↑
Current Address
Suspend Burst Read Cycle
X
H
L
↑
Current Address
Suspend Burst Write Cycle
H
X
H
L
↑
Current Address
Suspend Burst Write Cycle
WRITE TRUTH TABLE
Notes : 1. X means "Don
′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(
↑).
GW
BW
WEa
WEb
WEc
WEd
OPERATION
H
X
READ
H
L
H
READ
H
L
H
WRITE BYTE a
H
L
H
L
H
WRITE BYTE b
H
L
H
L
WRITE BYTE c and d
H
L
WRITE ALL BYTEs
L
X
WRITE ALL BYTEs
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2):
OPERATION
ZZ
OE
I/O STATUS
Sleep Mode
H
X
High-Z
Read
L
DQ
L
H
High-Z
Write
L
X
Din, High-Z
Deselected
L
X
High-Z
TRUTH TABLES
Notes
1. X means "Don
′t Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7A403601B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36/x32 & 256Kx18 Synchronous SRAM |
| K7A403601B-QC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36/x32 & 256Kx18 Synchronous SRAM |
| K7A403609A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36 & 256Kx18-Bit Synchronous Pipelined Burst SRAM |
| K7A403609B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36/x32 & 256Kx18 Synchronous SRAM |
| K7A403609B_06 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36/x32 & 256Kx18 Synchronous SRAM |
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