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參數(shù)資料
| 型號： | K6L0908V2A-TD850 |
| 元件分類： | SRAM |
| 英文描述： | 64K X 8 STANDARD SRAM, 85 ns, PDSO32 |
| 封裝： | 8 X 20 MM, TSOP1-32 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 193K |
| 代理商： | K6L0908V2A-TD850 |
K6L0908V2A, K6L0908U2A Family
CMOS SRAM
Revision 3.0
February 1998
6
Address
Data Out
Previous Data Valid
Data Valid
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, WE=VIH)
tAA
tRC
tOH
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Data Valid
High-Z
CS1
Address
OE
Data out
NOTES (READ CYCLE)
1.
tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
CS2
tOH
tAA
tOLZ
tLZ
tOHZ
tHZ(1,2)
tRC
tCO2
tOE
tCO1
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