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參數(shù)資料
| 型號： | JZ48F4L0QTY |
| 廠商： | Intel Corp. |
| 英文描述： | StrataFlash Wireless Memory |
| 中文描述： | 無線的StrataFlash存儲器 |
| 文件頁數(shù)： | 43/106頁 |
| 文件大?。?/td> | 1272K |
| 代理商： | JZ48F4L0QTY |
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Intel StrataFlash Wireless Memory (L18)
Datasheet
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
43
8.3
Power Supply Decoupling
Flash memory devices require careful power supply decoupling. Three basic power supply current
considerations are: 1) standby current levels; 2) active current levels; and 3) transient peaks
produced when CE# and OE# are asserted and deasserted.
When the device is accessed, many internal conditions change. Circuits within the device enable
charge-pumps, and internal logic states change at high speed. All of these internal activities
produce transient signals. Transient current magnitudes depend on the device outputs’ capacitive
and inductive loading. Two-line control and correct decoupling capacitor selection suppress
transient voltage peaks.
Because Intel
Multi-Level Cell (MLC) flash memory devices draw their power from V
CC
, VPP,
and VCCQ, each power connection should have a 0.1 μF ceramic capacitor connected to a
corresponding ground connection. High-frequency, inherently low-inductance capacitors should be
placed as close as possible to package leads.
Additionally, for every eight devices used in the system, a 4.7 μF electrolytic capacitor should be
placed between power and ground close to the devices. The bulk capacitor is meant to overcome
voltage droop caused by PCB trace inductance.
Figure 23.
Reset Operation Waveforms
(
A) Reset during
read mode
(B) Reset during
program or block erase
P1
≤
P2
(C) Reset during
program or block erase
P1
≥
P2
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
RST# [P]
RST# [P]
RST# [P]
Abort
Complete
Abort
Complete
V
CC
0V
V
CC
(D) VCC Power-up to
RST# high
P1
R5
P2
P3
P2
R5
R5
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| JZ48F4L0QTZ | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
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