參數(shù)資料
型號(hào)： JZ48F4L0QTY
廠商： Intel Corp.
英文描述： StrataFlash Wireless Memory
中文描述： 無線的StrataFlash存儲(chǔ)器
文件頁數(shù)： 31/106頁
文件大小： 1272K
代理商： JZ48F4L0QTY
Intel StrataFlash Wireless Memory (L18)
Datasheet
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
31
7.4
AC Read Specifications for 64-Mbit and 128-Mbit Densities
(V
CCQ
= 1.7 V – 2.0 V)
Num
Symbol
Parameter
Speed
–85
Units
Notes
Min
Max
Asynchronous Specifications
R1
R2
R3
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
PHQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
OH
t
EHEL
t
ELTV
t
EHTZ
t
GLTV
t
GLTX
t
GHTZ
Read cycle time
Address to output valid
CE# low to output valid
85
-
-
-
ns
ns
ns
6
85
85
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R15
R16
R17
OE# low to output valid
RST# high to output valid
CE# low to output in low-Z
OE# low to output in low-Z
CE# high to output in high-Z
OE# high to output in high-Z
Output hold from first occurring address, CE#, or OE# change
CE# pulse width high
CE# low to WAIT valid
CE# high to WAIT high Z
OE# low to WAIT valid
OE# low to WAIT in low-Z
OE# high to WAIT in high-Z
-
-
0
0
-
-
0
20
150
-
-
17
17
-
-
14
14
14
-
17
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2
1
1,3
1,2,3
1,3
14
-
-
-
0
-
1
1
1,3
1
1,3
1,3
Latching Specifications
R101
R102
R103
R104
R105
R106
R108
R111
t
AVVH
t
ELVH
t
VLQV
t
VLVH
t
VHVL
t
VHAX
t
APA
t
phvh
Address setup to ADV# high
CE# low to ADV# high
ADV# low to output valid
ADV# pulse width low
ADV# pulse width high
Address hold from ADV# high
Page address access
RST# high to ADV# high
7
-
-
ns
ns
ns
ns
ns
ns
ns
ns
1
10
-
7
7
7
-
30
85
-
-
-
25
-
1,6
1
1,4
1
1
Clock Specifications
R200
R201
R202
R203
f
CLK
t
CLK
t
CH/CL
t
FCLK/RCLK
CLK frequency
CLK period
CLK high/low time
CLK fall/rise time
-
54
-
-
3
MHz
ns
ns
ns
1,3
18.5
3.5
-
Synchronous Specifications
R301
R302
R303
R304
R305
R306
R307
R311
R312
t
AVCH/L
t
VLCH/L
t
ELCH/L
t
CHQV
/ t
CLQV
t
CHQX
t
CHAX
t
CHTV
t
CHVL
t
CHTX
Address setup to CLK
ADV# low setup to CLK
CE# low setup to CLK
CLK to output valid
Output hold from CLK
Address hold from CLK
CLK to WAIT valid
CLK Valid to ADV# Setup
WAIT Hold from CLK
7
7
7
-
3
7
-
0
3
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
14
-
-
14
-
-
1,5
1,4,5
1,5
1
1,5
NOTES:
1.
See
Figure 8, “AC Input/Output Reference Waveform” on page 28
for timing measurements and maximum allowable
input slew rate.
OE# may be delayed by up to t
ELQV
– t
GLQV
after CE#’s falling edge without impact to t
ELQV
.
Sampled, not 100% tested.
Address hold in synchronous burst mode is t
or t
VHAX
, whichever timing specification is satisfied first.
Applies only to subsequent synchronous reads.
The specifications in
Section 7.3
will
only
be used by customers (1) who desire a 1.35 to 2.0 V
operating range OR
(2) who desire to transition their host controller from a 1.7 V to 2.0 V V
CCQ
voltage now to a lower range in the future.
2.
3.
4.
5.
6.
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