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參數(shù)資料
| 型號： | JZ48F4L0BBZ |
| 廠商： | Intel Corp. |
| 英文描述： | StrataFlash Wireless Memory |
| 中文描述： | 無線的StrataFlash存儲器 |
| 文件頁數(shù)： | 45/106頁 |
| 文件大?。?/td> | 1272K |
| 代理商： | JZ48F4L0BBZ |
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Intel StrataFlash Wireless Memory (L18)
Datasheet
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
45
9.0
Device Operations
This section provides an overview of device operations. The system CPU provides control of all in-
system read, write, and erase operations of the device via the system bus. The on-chip Write State
Machine (WSM) manages all block-erase and word-program algorithms.
Device commands are written to the Command User Interface (CUI) to control all flash memory
device operations. The CUI does not occupy an addressable memory location; it is the mechanism
through which the flash device is controlled.
9.1
Bus Operations
CE#-low and RST#-high enable device read operations. The device internally decodes upper
address inputs to determine the accessed partition. ADV#-low opens the internal address latches.
OE#-low activates the outputs and gates selected data onto the I/O bus.
In asynchronous mode, the address is latched when ADV# goes high or continuously flows through
if ADV# is held low. In synchronous mode, the address is latched by the first of either the rising
ADV# edge or the next valid CLK edge with ADV# low (WE# and RST# must be VIH; CE# must
be VIL).
Bus cycles to/from the L18 device conform to standard microprocessor bus operations.
Table 7
summarizes the bus operations and the logic levels that must be applied to the device’s control
signal inputs.
Table 7.
Bus Operations Summary
Bus Operation
RST#
CLK
ADV#
CE#
OE#
WE#
WAIT
DQ[15:0]
Notes
Read
Asynchronous
V
IH
X
L
L
L
H
Deasserted
Output
Synchronous
V
IH
Running
L
L
L
H
Driven
Output
Burst Suspend
V
IH
Halted
X
L
H
H
High-Z
Output
Write
V
IH
X
L
L
H
L
High-Z
Input
1
Output Disable
V
IH
X
X
L
H
H
High-Z
High-Z
2
Standby
V
IH
X
X
H
X
X
High-Z
High-Z
2
Reset
V
IL
X
X
X
X
X
High-Z
High-Z
2,3
Notes:
1.
2.
3.
Refer to the
Table 8, “Command Bus Cycles” on page 47
for valid DQ[15:0] during a write operation.
X = Don’t Care (H or L).
RST# must be at V
SS
± 0.2 V to meet the maximum specified power-down current.
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PDF描述 |
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| JZ48F4L0BTY | StrataFlash Wireless Memory |
| JZ48F4L0BTZ | StrataFlash Wireless Memory |
| JZ48F4L0QBY | StrataFlash Wireless Memory |
| JZ48F4L0QBZ | StrataFlash Wireless Memory |
| JZ48F4L0QTY | StrataFlash Wireless Memory |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| JZ48F4L0BTY | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| JZ48F4L0BTZ | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| JZ48F4L0QBY | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| JZ48F4L0QBZ | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| JZ48F4L0QTY | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
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