- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384544 > ISPPAC-CLK5610V-01T100C (Lattice Semiconductor Corporation) In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer PDF資料下載
參數(shù)資料
| 型號： | ISPPAC-CLK5610V-01T100C |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| 中文描述： | 在系統(tǒng)可編程，零延遲時(shí)鐘發(fā)生器通用扇出緩沖器 |
| 文件頁數(shù)： | 34/47頁 |
| 文件大小： | 871K |
| 代理商： | ISPPAC-CLK5610V-01T100C |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當(dāng)前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁
Lattice Semiconductor
ispClock5600 Family Data Sheet
34
IEEE Standard 1149.1 Interface (JTAG)
Serial Port Programming Interface Communication with the ispClock5600 is facilitated via an IEEE 1149.1 test
access port (TAP). It is used by the ispClock5600 both as a serial programming interface, and for boundary scan
test purposes. A brief description of the ispClock5600 JTAG interface follows. For complete details of the reference
speci
fi
cation, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std.
1149.1-1990 (which now includes IEEE Std. 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the
ispClock5600. The TAP controller is a state machine driven with mode and clock inputs. Given in the correct
sequence, instructions are shifted into an instruction register which then determines subsequent data input, data
output, and related operations. Device programming is performed by addressing the con
fi
guration register, shifting
data in, and then executing a program con
fi
guration instruction, after which the data is transferred to internal
E
2
CMOS cells. It is these non-volatile cells that store the con
fi
guration or the ispClock5600. A set of instructions
are de
fi
ned that access all data registers and perform other internal control operations. For compatibility between
compliant devices, two data registers are mandated by the IEEE 1149.1 speci
fi
cation. Others are functionally spec-
i
fi
ed, but inclusion is strictly optional. Finally, there are provisions for optional data registers de
fi
ned by the manu-
facturer. The two required registers are the bypass and boundary-scan registers. Figure 30 shows how the
instruction and various data registers are organized in an ispClock5600.
Figure 30. ispClock5600 TAP Registers
TAP Controller Speci
fi
cs
The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether
an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a
small 16-state controller design. In a given state, the controller responds according to the level on the TMS input as
shown in Figure 31. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO)
becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-Reset, Run-
ADDRESS REGISTER (10 BITS)
E
2
CMOS
NON-VOLATILE
MEMORY
UES REGISTER (32 BITS)
IDCODE REGISTER (32 BITS)
BYPASS REGISTER (1 BIT)
INSTRUCTION REGISTER (8 BITS)
TEST ACCESS PORT (TAP)
LOGIC
OUTPUT
LATCH
TDI
TCK
TMS
TDO
B-SCAN REGISTER (56 BITS)
M
DATA REGISTER (90 BITS)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPPAC-CLK5620V-01T100C | LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA; Supply Voltage:24VDC; Wavelength:470nm |
| ISPPAC-CLK5620V-01T100I | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01T48C | Spot Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:160mA; Supply Voltage:30VDC; Wavelength:470nm |
| ISPPAC-CLK5620V-01T48C | LED Area Light; LED Color:Green; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:525nm |
| ISPPAC-CLK5610V-01T48I | LED Area Light; LED Color:Green; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA; Supply Voltage:24VDC; Wavelength:525nm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC-CLK5610V-01T100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01T48C | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 3.3V 10-320MHz RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPAC-CLK5610V-01T48I | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 PROGRAMMABLE ZERO DELAY CL GEN RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPAC-CLK5610V-01TN100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01TN100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。