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參數(shù)資料
| 型號： | ISPPAC-CLK5610V-01T100C |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| 中文描述： | 在系統(tǒng)可編程，零延遲時鐘發(fā)生器通用扇出緩沖器 |
| 文件頁數(shù)： | 10/47頁 |
| 文件大?。?/td> | 871K |
| 代理商： | ISPPAC-CLK5610V-01T100C |
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Lattice Semiconductor
ispClock5600 Family Data Sheet
10
Performance Characteristics – PLL
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
f
REF,
f
FBK
Reference and feedback input
frequency range
10
—
320
MHz
t
CLOCKHI,
t
CLOCKLO
t
RINP,
t
FINP
M
DIV
N
DIV
Reference and feedback input
clock HIGH and LOW times
1.25
—
—
ns
Reference and feedback input
rise and fall times
Measured between 20% and 80%
levels
—
—
5
ns
M-divider range
1
—
32
N-Divider range
1
—
32
f
PFD
Phase detector input frequency
range
2
10
—
320
MHz
f
VCO
V
DIV
VCO operating frequency
320
—
640
MHz
Output Divider range
Even integer values only
2
—
64
f
OUT
Output frequency range
1
Fine Skew Mode,
f
VCO
= 640MHz
Coarse Skew Mode,
f
VCO
= 640MHz
1000 cycle sample
3
10
—
320
MHz
5
—
160
MHz
t
JIT
(cc)
t
JIT
(per)
Output adjacent-cycle jitter
Output period jitter
—
45
60
ps (p-p)
10000 cycle sample
3
—
8
10
ps (RMS)
t
φ
Static phase offset
PFD input frequency
≥
100MHz
7
PFD input frequency <100MHz
7
-375
-75
225
ps
-37.5
—
22.5
mUI
6
t
DELAY
Reference clock to output delay Internal feedback mode
7
0.3
0.45
0.6
ns
DC
ERR
Output duty cycle error (see
Table 3 for nominal values)
4
Output type LVDS, V
CCO
= 3.3V
5
Output type LVCMOS 3.3V
5
f
OUT
>100 MHz
—
—
260
ps
—
—
300
ps
t
PDBYPASS
Reference clock to output
propagation delay
M=1, V=2
—
6
—
ns
t
L
PLL Lock time
From Power-up event
—
150
500
μs
From Reset event
—
15
50
μs
PSR
Power supply rejection, period
jitter vs. power supply noise
f
IN
= f
OUT
= 100MHz
VCCA = VCCD = VCCO modulated
with 100kHz sinusoidal stimulus
—
0.05
—
1. In PLL Bypass mode (PLL_BYPASS = HIGH), output will support frequencies down to 0Hz (divider chain is a fully static design).
2. Dividers should be set so that they provide the phase detector with signals of 10MHz or greater for loop stability.
3. f
IN
= f
OUT
= 100 MHz, M = N = 1, V = 6, output type LVPECL.
4. Variation in duty cycle expressed in ps. To obtain duty cycle percentage error (%
ERR
) for a given output frequency (f
OUT
), %
ERR
= 100 x
f
OUT
x DC
ERR.
5. See Figures 3-5 for output loads.
6. milli-Unit Interval
7. Input and outputs LVPECL mode
ps(RMS)
mV(p-p)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPPAC-CLK5620V-01T100C | LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA; Supply Voltage:24VDC; Wavelength:470nm |
| ISPPAC-CLK5620V-01T100I | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01T48C | Spot Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:160mA; Supply Voltage:30VDC; Wavelength:470nm |
| ISPPAC-CLK5620V-01T48C | LED Area Light; LED Color:Green; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:525nm |
| ISPPAC-CLK5610V-01T48I | LED Area Light; LED Color:Green; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA; Supply Voltage:24VDC; Wavelength:525nm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC-CLK5610V-01T100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01T48C | 功能描述:時鐘驅(qū)動器及分配 3.3V 10-320MHz RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPAC-CLK5610V-01T48I | 功能描述:時鐘驅(qū)動器及分配 PROGRAMMABLE ZERO DELAY CL GEN RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPAC-CLK5610V-01TN100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01TN100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
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