參數(shù)資料
型號(hào)： ISPPAC-CLK5610V-01T100C
廠(chǎng)商： Lattice Semiconductor Corporation
英文描述： In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
中文描述： 在系統(tǒng)可編程，零延遲時(shí)鐘發(fā)生器通用扇出緩沖器
文件頁(yè)數(shù)： 22/47頁(yè)
文件大小： 871K
代理商： ISPPAC-CLK5610V-01T100C
Lattice Semiconductor
ispClock5600 Family Data Sheet
22
Note that while a
fl
oating 100
resistor forms a complete termination for an LVDS signal line, additional circuitry
may be required to satisfactorily terminate a differential LVPECL signal. This is because a true bipolar LVPECL out-
put driver typically requires an external DC ‘pull-down’ path to a V
TERM
termination voltage (typically VCC-2V) to
properly bias its open emitter output stage. When interfacing to an LVPECL input signal, the ispClock5600’s inter-
nal termination resistors should not be used for this pull-down function, as they may be damaged from excessive
current. The pull-down should be implemented with external resistors placed close to the LVPECL driver
(Figure 18)
Figure 18. LVPECL Input Receiver Configuration
Please note that while the above discussions specify using 50
termination impedances, the actual impedance
required to properly terminate the transmission line and maintain good signal integrity may vary from this ideal. The
actual impedance required will be a function of the driver used to generate the signal and the transmission medium
used (PCB traces, connectors and cabling). The ispClock5600’s ability to adjust input impedance over a range of
40
to 70
allows the user to adapt his circuit to non-ideal behaviors from the rest of the system without having to
swap out components.
Output Drivers
The ispClock5600 provide banks of con
fi
gurable, internally-terminated high-speed dual-output line drivers. The
ispClock5610 provides
fi
ve driver banks, while the ispClock5620 provides ten. Each of these driver banks may be
con
fi
gured to provide either a single differential output signal, or a pair of single-ended output signals. Programma-
ble internal source-series termination allows the ispClock5600 to be matched to transmission lines with imped-
ances ranging from 40 to 70 Ohms. The outputs may be independently enabled or disabled, either from E
2
CMOS
con
fi
guration or by external control lines. Additionally, each can be independently programmed to provide a
fi
xed
amount of signal delay or skew, allowing the user to compensate for the effects of unequal PCB trace lengths or
loading effects. Figure 19 shows a block diagram of a typical ispClock5600 output driver bank and associated skew
control.
Because of the high edge rates which can be generated by the ispClock5600’s clock output drivers, the VCCO
power supply pin for each output bank should be individually bypassed. Low ESR capacitors with values ranging
from 0.01 to 0.1 μF may be used for this purpose. Each bypass capacitor should be placed as close to its respec-
tive output bank power pins (VCCO and GNDO) pins as is possible to minimize interconnect length and associated
parasitic inductances.
50
CLOSED
REFA-
REFA+
REFVTT
Differential
Receiver
+Signal In
CLOSED
-Signal In
50
No Connect
LVPECL
Driver
ispClock5600
R
PD
R
PD
V
TERM
相關(guān)PDF資料
PDF描述
ISPPAC-CLK5620V-01T100C LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA; Supply Voltage:24VDC; Wavelength:470nm
ISPPAC-CLK5620V-01T100I In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
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ISPPAC-CLK5620V-01T48C LED Area Light; LED Color:Green; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:525nm
ISPPAC-CLK5610V-01T48I LED Area Light; LED Color:Green; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA; Supply Voltage:24VDC; Wavelength:525nm
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPAC-CLK5610V-01T100I 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5610V-01T48C 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 3.3V 10-320MHz RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類(lèi)型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPAC-CLK5610V-01T48I 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 PROGRAMMABLE ZERO DELAY CL GEN RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類(lèi)型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPAC-CLK5610V-01TN100C 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5610V-01TN100I 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
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