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參數(shù)資料
| 型號： | ISPPAC-CLK55xx |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| 中文描述： | 在系統(tǒng)可編程時鐘發(fā)生器與通用扇出緩沖器 |
| 文件頁數(shù)： | 30/43頁 |
| 文件大?。?/td> | 867K |
| 代理商： | ISPPAC-CLK55XX |
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Lattice Semiconductor
ispClock5500 Family Data Sheet
30
In-System Programming
The ispClock5500 is an In-System Programmable (ISP) device. This is accomplished by integrating all E
2
CMOS
con
fi
guration control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant serial JTAG
interface at normal logic levels. Once a device is programmed, all con
fi
guration information is stored on-chip, in
non-volatile E
2
CMOS memory cells. The speci
fi
cs of the IEEE 1149.1 serial interface and all ispClock5500 instruc-
tions are described in the JTAG interface section of this data sheet.
User Electronic Signature
A user electronic signature (UES) feature is included in the E
2
CMOS memory of the ispClock5500. This consists of
32 bits that can be con
fi
gured by the user to store unique data such as ID codes, revision numbers or inventory
control data. The speci
fi
cs this feature are discussed in the IEEE 1149.1 serial interface section of this data sheet.
Electronic Security
An electronic security “fuse” (ESF) bit is provided in every ispClock5500 device to prevent unauthorized readout of
the E
2
CMOS con
fi
guration bit patterns. Once programmed, this cell prevents further access to the functional user
bits in the device. This cell can only be erased by reprogramming the device, so the original con
fi
guration can not
be examined once programmed. Usage of this feature is optional. The speci
fi
cs of this feature are discussed in the
IEEE 1149.1 serial interface section of this data sheet.
Production Programming Support
Once a
fi
nal con
fi
guration is determined, an ASCII format JEDEC
fi
le can be created using the PAC-Designer soft-
ware. Devices can then be ordered through the usual supply channels with the user’s speci
fi
c con
fi
guration already
preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production
programming equipment, giving customers a wide degree of freedom and
fl
exibility in production planning.
Evaluation Fixture
Included in the basic ispClock5500 Design Kit is an engineering prototype board that can be connected to the par-
allel port of a PC using a Lattice ispDOWNLOAD
cable. It demonstrates proper layout techniques for the
ispClock5500 and can be used in real time to check circuit operation as part of the design process. Input and out-
put connections (SMA connectors for all RF signals) are provided to aid in the evaluation of the ispClock5500 for a
given application. (Figure 27).
Figure 27. Download from a PC
Part Number
Description
PAC-SYSTEMCLK5520
PACCLK5520
-
EV
Complete system kit, evaluation board, ispDOWNLOAD cable and software.
Evaluation board only, with components, fully assembled.
ispDownload
Cable (6')
4
Other
System
Circuitry
ispClock5500
Device
PAC-Designer
Software
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPPAC-CLK5510V | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5510V-01T48C | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5510V-01T48I | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5520V-01T100C | LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:470nm |
| ISPPAC-CLK5520V-01T100I | Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:800mA; Supply Voltage:24VDC; Wavelength:470nm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPACCLK5610AV-01T100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
| ISPPACCLK5610AV-01T100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
| ispPAC-CLK5610AV-01T48C | 功能描述:時鐘驅(qū)動器及分配 ISP 0 Delay Clock Ge n w/Unv Fan-Out Buf RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5610AV-01T48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
| ispPAC-CLK5610AV-01T48I | 功能描述:時鐘驅(qū)動器及分配 ISP 0 Dlay Clck Gen w/Unv Fan-Out Buf I RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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