參數(shù)資料
型號(hào): ISPPAC-CLK5510V
廠商: Lattice Semiconductor Corporation
英文描述: In-System Programmable Clock Generator with Universal Fan-Out Buffer
中文描述: 在系統(tǒng)可編程時(shí)鐘發(fā)生器與通用扇出緩沖器
文件頁(yè)數(shù): 7/43頁(yè)
文件大?。?/td> 867K
代理商: ISPPAC-CLK5510V
Lattice Semiconductor
ispClock5500 Family Data Sheet
7
Switching Characteristics – Timing Adders for I/O Modes
Output Rise and Fall Times – Typical Values
1, 2
Adder Type
t
IOI
Input Adders
2
LVTTL_in
Base Parameter(s)
Description
Min.
Typ.
Max.
Units
Using LVTTL Standard
0
ns
LVCMOS18_in
Using LVCMOS 1.8V Standard
0
ns
LVCMOS25_in
Using LVCMOS 2.5V Standard
0
ns
LVCMOS33_in
Using LVCMOS 3.3V Standard
0
ns
SSTL2_in
Using SSTL2 Standard
0.4
ns
SSTL3_in
Using SSTL3 Standard
0.4
ns
HSTL_in
Using HSTL Standard
0.4
ns
LVDS_in
Using LVDS Standard
1.8
ns
LVPECL_in
t
IOO
Output Adders
1, 3
LVTTL_out
Using LVPECL Standard
1.8
ns
Output Con
fi
gured as LVTTL Buffer
0.1
ns
LVCMOS18_out
Output Con
fi
gured as LVCMOS 1.8V Buffer
0.1
ns
LVCMOS25_out
Output Con
fi
gured as LVCMOS 2.5V Buffer
0.1
ns
LVCMOS33_out
Output Con
fi
gured as LVCMOS 3.3V Buffer
0.1
ns
SSTL2_out
Output Con
fi
gured as SSTL2 Buffer
0.1
ns
SSTL3_out
Output Con
fi
gured as SSTL3 Buffer
0.1
ns
HSTL_out
Output Con
fi
gured as HSTL Buffer
0.1
ns
LVDS_out
Output Con
fi
gured as LVDS Buffer
0.1
ns
LVPECL_out
t
IOS
Output Slew Rate Adders
1
Slew_1
Output Con
fi
gured as LVPECL Buffer
0
ns
Output Slew_1 (Fastest)
0
ps
Slew_2
Output Slew_2
330
ps
Slew_3
Output Slew_3
660
ps
Slew_4
Output Slew_4 (Slowest)
1320
ps
1. Measured under standard output load conditions – see Figures 3-5.
2. All input adders referenced to LVTTL.
3. All output adders referenced to LVPECL.
Output Type
Slew 1 (Fastest)
Slew 2
Slew 3
Slew 4 (Slowest)
Units
t
R
t
F
t
R
t
F
t
R
t
F
t
R
t
F
LVTTL
0.65
0.45
0.85
0.60
1.20
0.90
1.75
1.30
ns
LVCMOS 1.8V
0.90
0.40
1.05
0.50
1.40
0.80
2.00
1.20
ns
LVCMOS 2.5V
0.70
0.40
0.90
0.55
1.20
0.85
1.80
1.20
ns
LVCMOS 3.3V
0.65
0.45
0.85
0.60
1.20
0.90
1.75
1.30
ns
SSTL2
0.55
0.35
0.85
0.45
1.45
0.65
2.30
1.20
ns
SSTL3
0.50
0.40
0.80
0.50
1.45
0.75
2.30
1.35
ns
HSTL
LVDS
3
LVPECL
3
0.65
0.35
0.85
0.45
1.30
0.65
1.90
1.25
ns
0.60
0.60
ns
0.65
0.60
ns
1. See Figures 3-5 for test conditions.
2. Measured between 20% and 80% points.
3. Only the ‘fastest’ slew rate is available in LVDS and LVPECL modes.
相關(guān)PDF資料
PDF描述
ISPPAC-CLK5510V-01T48C In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5510V-01T48I In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5520V-01T100C LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:470nm
ISPPAC-CLK5520V-01T100I Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:800mA; Supply Voltage:24VDC; Wavelength:470nm
ISPPAC-CLK5520V-01TN100I LED Area Light; LED Color:Infrared; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:150mA; Supply Voltage:24VDC; Wavelength:940nm
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPACCLK5510V-01T100C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPACCLK5510V-01T100I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5510V-01T48C 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 PROGRAMMABLE CLOCK GENERATOR RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPACCLK5510V-01T48C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5510V-01T48I 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 PROGRAMMABLE CLOCK GENERATOR RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel