- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384544 > ISPPAC-CLK5510V (Lattice Semiconductor Corporation) In-System Programmable Clock Generator with Universal Fan-Out Buffer PDF資料下載
參數(shù)資料
| 型號： | ISPPAC-CLK5510V |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| 中文描述： | 在系統(tǒng)可編程時鐘發(fā)生器與通用扇出緩沖器 |
| 文件頁數(shù)： | 19/43頁 |
| 文件大?。?/td> | 867K |
| 代理商： | ISPPAC-CLK5510V |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁
Lattice Semiconductor
ispClock5500 Family Data Sheet
19
One important point to note is that the termination supplies must have low impedance and be able to both source
and sink current without experiencing
fl
uctuations. These requirements generally preclude the use of a resistive
divider network, which has an impedance comparable to the resistors used, or of commodity-type linear voltage
regulators, which can only source current. The best way to develop the necessary termination voltages is with a
regulator speci
fi
cally designed for this purpose. Because SSTL and HSTL logic is commonly used for high-perfor-
mance memory busses, a suitable termination voltage supply is often already available in the system.
Figure 14. SSTL2, SSTL3, HSTL Receiver Configuration
Differential HSTL and SSTL
HSTL and SSTL are sometimes used in a differential form, especially for distributing clocks in high-speed memory
systems. Figure 15 shows how ispClock5500 reference input should be con
fi
gured for accepting these standards.
The major difference between the differential and single-ended forms of these logic standards is that in the differen-
tial cases, the REFA- input is used as a signal input, not a reference level, and that both terminating resistors are
engaged and set to 50
.
Figure 15. Differential HSTL/SSTL Receiver Configuration
50
CLOSED
REFA-
REFA+
REFVTT
VTT
Differential
Receiver
VREF IN
Signal In
ispClock5500
OPEN
50
CLOSED
REFA-
REFA+
REFVTT
Differential
Receiver
+Signal In
ispClock5500
CLOSED
-Signal In
50
VTT
相關PDF資料 |
PDF描述 |
|---|---|
| ISPPAC-CLK5510V-01T48C | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5510V-01T48I | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5520V-01T100C | LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:470nm |
| ISPPAC-CLK5520V-01T100I | Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:800mA; Supply Voltage:24VDC; Wavelength:470nm |
| ISPPAC-CLK5520V-01TN100I | LED Area Light; LED Color:Infrared; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:150mA; Supply Voltage:24VDC; Wavelength:940nm |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPACCLK5510V-01T100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPACCLK5510V-01T100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5510V-01T48C | 功能描述:時鐘驅動器及分配 PROGRAMMABLE CLOCK GENERATOR RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5510V-01T48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5510V-01T48I | 功能描述:時鐘驅動器及分配 PROGRAMMABLE CLOCK GENERATOR RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。