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參數(shù)資料
| 型號： | ISPPAC-CLK5510V |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| 中文描述： | 在系統(tǒng)可編程時(shí)鐘發(fā)生器與通用扇出緩沖器 |
| 文件頁數(shù)： | 20/43頁 |
| 文件大小： | 867K |
| 代理商： | ISPPAC-CLK5510V |
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Lattice Semiconductor
ispClock5500 Family Data Sheet
20
LVDS/Differential LVPECL
The receiver should be set to LVDS or LVPECL mode as required and both termination resistors should be
engaged and set to 50
. The REFVTT pin, however, should be left unconnected. This creates a
fl
oating 100
dif-
ferential termination resistance across the input terminals. The LVDS termination con
fi
guration is shown in
Figure 16.
Figure 16. LVDS Input Receiver Configuration
Note that while a
fl
oating 100
resistor forms a complete termination for an LVDS signal line, additional circuitry
may be required to satisfactorily terminate a differential LVPECL signal. This is because a true bipolar LVPECL out-
put driver typically requires an external DC ‘pull-down’ path to a V
TERM
termination voltage (typically VCC-2V) to
properly bias its open emitter output stage. When interfacing to an LVPECL input signal, the ispClock5500’s inter-
nal termination resistors should not be used for this pull-down function, as they may be damaged from excessive
current. The pull-down should be implemented with external resistors placed close to the LVPECL driver
(Figure 17)
Figure 17. LVPECL Input Receiver Configuration
50
CLOSED
REFA-
REFA+
REFVTT
Differential
Receiver
+Signal In
CLOSED
-Signal In
50
No Connect
LVDS
Driver
ispClock5500
50
CLOSED
REFA-
REFA+
REFVTT
Differential
Receiver
+Signal In
CLOSED
-Signal In
50
No Connect
LVPECL
Driver
ispClock5500
R
PD
R
PD
V
TERM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPPAC-CLK5510V-01T48C | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5510V-01T48I | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5520V-01T100C | LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:470nm |
| ISPPAC-CLK5520V-01T100I | Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:800mA; Supply Voltage:24VDC; Wavelength:470nm |
| ISPPAC-CLK5520V-01TN100I | LED Area Light; LED Color:Infrared; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:150mA; Supply Voltage:24VDC; Wavelength:940nm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPACCLK5510V-01T100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPACCLK5510V-01T100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5510V-01T48C | 功能描述:時(shí)鐘驅(qū)動器及分配 PROGRAMMABLE CLOCK GENERATOR RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5510V-01T48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5510V-01T48I | 功能描述:時(shí)鐘驅(qū)動器及分配 PROGRAMMABLE CLOCK GENERATOR RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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