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參數(shù)資料
| 型號(hào)： | ISPPAC-CLK5320S-01TN64I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 15/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BUFFER FANOUT 20OUTPUT 64TQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | ispClock™ |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送，零延遲緩沖器 |
| PLL： | 帶旁路 |
| 輸入： | HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL |
| 輸出： | eHSTL，HSTL，LVCMOS，LVTTL，SSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:20 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 267MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP（10x10） |
| 包裝： | 托盤 |
| 其它名稱： | 220-1003 |
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Lattice Semiconductor
ispClock5300S Family Data Sheet
22
LVTTL (3.3V), LVCMOS (1.8V, 2.5V, 3.3V)
The receiver should be set to LVCMOS or LVTTL mode, and the input signal can be connected to either the REFA
or REFB pins. CMOS transmission lines are generally source terminated, so all termination resistors should be set
to the OPEN state. Figure 15 shows the proper conguration. Please note that because switching thresholds are
different for LVCMOS running at 1.8V, there is a separate conguration setting for this particular standard. Unused
reference inputs and VTT pins should be grounded.
Figure 15. LVCMOS/LVTTL Input Receiver Conguration
HSTL, eHSTL, SSTL2, SSTL3
The receiver should be set to HSTL/SSTL mode, and the input signal can be connected to the REFA or REFB ter-
minal of the input pair and the associated VTT_REFA or VTT_REFB terminal should be tied to a VTT termination
supply. The terminating resistor should be set to 50Ω and the engaging switch should be closed. Figure 16 shows
an appropriate conguration. Refer to the “Recommended Operating Conditions - Supported Logic Standards”
table in this data sheet for suitable values of VREF and VTT.
One important point to note is that the termination supplies must have low impedance and be able to both source
and sink current without experiencing uctuations. These requirements generally preclude the use of a resistive
divider network, which has an impedance comparable to the resistors used, or of commodity-type linear voltage
regulators, which can only source current. The best way to develop the necessary termination voltages is with a
regulator specically designed for this purpose. Because SSTL and HSTL logic is commonly used for high-perfor-
mance memory busses, a suitable termination voltage supply is often already available in the system.
Figure 16. SSTL2, SSTL3, eHSTL, HSTL Receiver Conguration
Differential LVPECL/LVDS
The receiver should be set to LVDS or LVPECL mode as required and both termination resistors should be
engaged and set to 50Ω. The VTT_REFA and VTT_REFB pins, however, should be connected. This creates a oat-
ing 100Ω differential termination resistance across the input terminals. The LVDS termination conguration is
shown in Figure 17.
Note: the REFSEL pin should be grounded when the input receiver is congured as differential.
Single-ended
Receiver
Open
GND
RT
VTT_REFA /
VTT_REFB
REFA_REFP /
REFB_REFN
Single-ended
Receiver
Closed
50
VTT_REFA /
VTT_REFB
REFA_REFP /
REFB_REFN
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPACCLK5320S-01TN64I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ispPAC-CLK5406D-01SN48C | 功能描述:鎖相環(huán) - PLL 3.3V 6 diff. outputs RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| ispPAC-CLK5406D-01SN48I | 功能描述:鎖相環(huán) - PLL 3.3V 6 diff. outputs RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| ispPAC-CLK5410D-01SN64C | 功能描述:鎖相環(huán) - PLL 3.3V 10 diff. outputs RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| ispPAC-CLK5410D-01SN64I | 功能描述:鎖相環(huán) - PLL 3.3V 10 diff. outputs RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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