在线天堂中文www官网,亚洲另类无码一区二区三区

您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9222 > ISPPAC-CLK5320S-01TN64I (Lattice Semiconductor Corporation)IC BUFFER FANOUT 20OUTPUT 64TQFP PDF資料下載

參數(shù)資料

型號(hào)：	ISPPAC-CLK5320S-01TN64I
廠商：	Lattice Semiconductor Corporation
文件頁(yè)數(shù)：	12/56頁(yè)
文件大?。?/td>	0K
描述：	IC BUFFER FANOUT 20OUTPUT 64TQFP
標(biāo)準(zhǔn)包裝：	160
系列：	ispClock™
類型：	時(shí)鐘發(fā)生器，扇出配送，零延遲緩沖器
PLL：	帶旁路
輸入：	HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL
輸出：	eHSTL，HSTL，LVCMOS，LVTTL，SSTL
電路數(shù)：	1
比率 - 輸入:輸出：	2:20
差分 - 輸入:輸出：	是/無(wú)
頻率 - 最大：	267MHz
除法器/乘法器：	是/無(wú)
電源電壓：	3 V ~ 3.6 V
工作溫度：	-40°C ~ 85°C
安裝類型：	表面貼裝
封裝/外殼：	64-LQFP
供應(yīng)商設(shè)備封裝：	64-TQFP（10x10）
包裝：	托盤
其它名稱：	220-1003

Lattice Semiconductor

ispClock5300S Family Data Sheet

General Description

The ispClock5300S is an in-system-programmable zero delay universal fan-out buffer for use in clock distribution

applications. The ispClock5312S, the rst member of the ispClock5300S family, provides up to 12 single-ended

ultra low skew outputs. Each pair of outputs may be independently congured to support separate I/O standards

(LVTTL, LVCMOS -3.3V, 2.5V, 1.8, SSTL, HSTL) and output frequency. In addition, each output provides indepen-

dent programmable control of termination, slew-rate, and timing skew. All conguration information is stored on-

chip in non-volatile E

2CMOS memory.

The ispClock5300S devices provide extremely low propagation delay (zero-delay) from input to output using the

on-chip low jitter high-performance PLL. A set of three programmable 5-bit counters can be used to generate three

frequencies derived from the PLL clock. These counters are programmable in powers of 2 only (1, 2, 4, 8, 16, 32).

The clock output from any of the V-dividers can then be routed to any clock output pin through the output routing

matrix. The output routing matrix, in addition, also enables routing of reference clock inputs directly to any output.

The ispClock5300S device can be congured to operate in four modes: zero delay buffer mode, dual non-zero

delay buffer mode, non-zero delay buffer mode with output dividers, and combined zero-delay and non-zero delay

buffer mode.

The core functions of all members of the ispClock5300S family are identical. Table 1 summarizes the

ispClock5300S device family.

Table 1. ispClock5300S Family

Figure 1. ispClock5304S Functional Block Diagram

Device

Number of Programmable

Clock Inputs

Number of Programmable

Single-Ended Outputs

ispClock5320S