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參數(shù)資料
| 型號(hào)： | ISPLSI1024EA-200LT100 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | In-System Programmable High Density PLD |
| 中文描述： | EE PLD, 6 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 2/13頁(yè) |
| 文件大?。?/td> | 162K |
| 代理商： | ISPLSI1024EA-200LT100 |
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2
Specifications
ispLSI 1024EA
Functional Block Diagram
Figure 1. ispLSI 1024EA Functional Block Diagram
The device also has 48 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered in-
put, latched input, output or bi-directional
I/O pin with 3-state control. The signal levels are TTL
compatible voltages and the output drivers can source 4
mA or sink 8 mA. Each output can be programmed
independently for fast or slow output slew rate to mini-
mize overall output switching noise. By connecting the
VCCIO pin to a common 5V or 3.3V power supply, I/O
output levels can be matched to 5V or 3.3V-compatible
voltages.
Eight GLBs, 16 I/O cells, dedicated inputs (if available)
and one ORP are connected together to make a
Megablock (Figure 1). The outputs of the eight GLBs are
connected to a set of 16 universal I/O cells by the ORP.
Each ispLSI 1024EA device contains three Megablocks.
The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1024EA device are selected using
the Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (C0 on the ispLSI
1024EA device). The logic of this GLB allows the user to
create an internal clock from a combination of internal
signals within the device.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 1024EA are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.
RESET
Global
Routing
Pool
(GRP)
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
Clock
Distribution
Network
C7
C6
C5
C4
C3
C2
C1
C0
A0
A1
A2
A3
A4
A5
A6
A7
Generic
Logic Blocks
(GLBs)
Megablock
O
O
Output Routing Pool (ORP)
Input Bus
VCCIO
l
l
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O 35
I/O 34
I/O 33
I/O 32
I/O 0
I/O 1
I/O 2
I/O 3
I/O 12
I/O 13
I/O 14
I/O 15
TDI
TDO
TMS
TCK
I/O 8
I/O 9
I/O 10
I/O 11
I/O 4
I/O 5
I/O 6
I/O 7
I/O 47
I/O 46
I/O 45
I/O 44
GOE 1/IN 5
GOE 0/IN 4
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
Y
Y
Y
Y
B0
B1
B2
B3
B4
B5
B6
B7
0139B/1024EA
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相關(guān)代理商/技術(shù)參數(shù) |
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| ISPLSI1032 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
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| ISPLSI1032-60 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1032-60LG | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1032-60LG/833 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
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