- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384536 > ISPGDX80VA-9T100I (LATTICE SEMICONDUCTOR CORP) In-System Programmable 3.3V Generic Digital CrosspointTM PDF資料下載
參數(shù)資料
| 型號： | ISPGDX80VA-9T100I |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | In-System Programmable 3.3V Generic Digital CrosspointTM |
| 中文描述： | EE PLD, 9 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 7/27頁 |
| 文件大小： | 346K |
| 代理商： | ISPGDX80VA-9T100I |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁
7
Specifications
ispGDX80VA
Figure 6. Data Bus Byte Swapper
Figure 7. Four-Port Memory Interface
C
D
D
OEA OEB
I/OA
D0-7
D8-15
D8-15
D0-7
I/OB
XCVR
OEA OEB
I/OA
I/OB
XCVR
OEA OEB
I/OA
I/OB
XCVR
OEA OEB
I/OA
I/OB
XCVR
B
B
B
B
Port #1
OE1
Memory
Port
OEM
SEL0
SEL1
To
Memory
Port #2
OE2
Port #3
OE3
Note: All OE and SEL lines driven by external arbiter logic (not shown).
Port #4
OE4
4-to-1
16-Bit MUX
Bidirectional
Figure 5. Address Demultiplex/Data Buffering
C
M
D
Q
CLK
OEA
OEB
I/OA
I/OB
Address
Buffered
Data
To Memory/
Peripherals
XCVR
Address
Latch
Applications (Continued)
Designing with the ispGDXVA
As mentioned earlier, this architecture satisfies the PRSI
class of applications without restrictions: any I/O pin as a
single input or bidirectional can drive any other I/O pin as
output.
For the case of PDP applications, the designer does have
to take into consideration the limitations on pins that can
be used as control (MUX0, MUX1, OE, CLK) or data
(MUXA-D) inputs. The restrictions on control inputs are
not likely to cause any major design issues because the
input possibilities span 25% of the total pins.
The MUXA-D input partitioning requires that designers
consciously assign pinouts so that MUX inputs are in the
appropriate, disjoint groups. For example, since the
MUXA group includes I/O A0-A19 (80 I/O device), it is not
possible to use I/O A0 and I/O A9 in the same MUX
function. As previously discussed, data path functions
will be assigned early in the design process and these
restrictions are reasonable in order to optimize speed
and cost.
User Electronic Signature
The ispGDXVA Family includes dedicated User Elec-
tronic Signature (UES) E
2
CMOS storage to allow users
to code design-specific information into the devices to
identify particular manufacturing dates, code revisions,
or the like. The UES information is accessible through
the boundary scan programming port via a specific com-
mand. This information can be read even when the
security cell is programmed.
Security
The ispGDXVA Family includes a security feature that
prevents reading the device program once set. Even
when set, it does not inhibit reading the UES or device ID
code. It can be erased only via a device bulk erase.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPL1048E-125LQI | High-Density Programmable Logic |
| ISPL1048E-100LQ | High-Density Programmable Logic |
| ISPL1048E-100LQI | High-Density Programmable Logic |
| ISPL1048E-100LT | High-Density Programmable Logic |
| ISPL1048E-100LTI | High-Density Programmable Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPGDX80VA-9TN100I | 功能描述:模擬和數(shù)字交叉點(diǎn) IC PROGRAMMABLE GEN DIG CROSSPOINT RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube |
| ISPGDXTMFAMILY | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Generic Digital CrosspointTM |
| ISPHEADER01 | 制造商:Xeltek Inc 功能描述:ISP10/D10 |
| ISPICR1 | 功能描述:ADAPTER IN-CIRCUIT PROGRAMMING RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 配件 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program RoHS指令信息:IButton RoHS Compliance Plan 標(biāo)準(zhǔn)包裝:1 系列:- 附件類型:USB 至 1-Wire? RJ11 適配器 適用于相關(guān)產(chǎn)品:1-Wire? 設(shè)備 產(chǎn)品目錄頁面:1429 (CN2011-ZH PDF) |
| ISPL1048E-100LQ | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。