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參數(shù)資料
| 型號(hào)： | ISPGDX80VA-9T100I |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | In-System Programmable 3.3V Generic Digital CrosspointTM |
| 中文描述： | EE PLD, 9 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 3/27頁 |
| 文件大?。?/td> | 346K |
| 代理商： | ISPGDX80VA-9T100I |
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3
Specifications
ispGDX80VA
Architecture
The ispGDXVA architecture is different from traditional
PLD architectures, in keeping with its unique application
focus. The block diagram is shown below. The program-
mable interconnect consists of a single Global Routing
Pool (GRP). Unlike ispLSI devices, there are no pro-
grammable logic arrays on the device. Control signals for
OEs, Clocks/Clock Enables and MUX Controls must
come from designated sets of I/O pins. The polarity of
these signals can be independently programmed in each
I/O cell.
Each I/O cell drives a unique pin. The OE control for each
I/O pin is independent and may be driven via the GRP by
one of the designated I/O pins (I/O-OE set). The I/O-OE
set consists of 25% of the total I/O pins. Boundary Scan
test is supported by dedicated registers at each I/O pin.
In-system programming is accomplished through the
standard Boundary Scan protocol.
The various I/O pin sets are also shown in the block
diagram below. The A, B, C, and D I/O pins are grouped
together with one group per side.
I/O Architecture
Each I/O cell contains a 4:1 dynamic MUX controlled by
two select lines as well as a 4x4 crossbar switch con-
trolled by software for increased routing flexiability (Figure
1). The four data inputs to the MUX (called M0, M1, M2,
and M3) come from I/O signals in the GRP and/or
adjacent I/O cells. Each MUX data input can access one
quarter of the total I/Os. For example, in an 80-I/O
ispGDXVA, each data input can connect to one of 20 I/O
pins. MUX0 and MUX1 can be driven by designated I/O
pins called MUXsel1 and MUXsel2. Each MUXsel input
covers 25% of the total I/O pins (e.g. 20 out of 80). MUX0
and MUX1 can be driven from either MUXsel1 or MUXsel2.
Figure 1. ispGDXVA I/O Cell and GRP Detail (80 I/O Device)
I/OCell 0
I/O Cell 1
I/O Cell 38
I/O Cell 39
40 I/O Cells
Boundary
Scan Cell
Bypass Option
I/O Cell N
Register
or Latch
I/O
Pin
Prog.
(VCCIO)
Prog. Slew Rate
D
CLK
A
B
Reset
Q
4-to-1 MUX
M0
M1
M2
M3
MUX0
80 Input GRP
Outputs Horizontal
I/O Cell 79
I/O Cell 78
I/O Cell 41
I/O Group A
I/O Group B
I/O Group C
I/O Group D
4x4
Crossbar
Switch
MUX1
Global
Reset
I/O Cell 40
40 I/O Cells
ispGDXVA architecture enhancements over ispGDX (5V)
E
2
CMOS
Programmable
Interconnect
Logic
“
0
”
Logic
“
1
”
80 I/O Inputs
C
R
ClocY0-Y3
BProg.
Latch
CLK_EN
oFrom MUX Outputs
oFrom MUX Outputs
ITo 2 Adjacent
To 2 Adjacent
I/O Cells below
Prog. Open Drain
2.5V/3.3V Output
N+1
N+2
N-1
N-2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ISPGDX80VA-9TN100I | 功能描述:模擬和數(shù)字交叉點(diǎn) IC PROGRAMMABLE GEN DIG CROSSPOINT RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube |
| ISPGDXTMFAMILY | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Generic Digital CrosspointTM |
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| ISPL1048E-100LQ | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
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