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參數(shù)資料
| 型號： | ISPGDX80VA-9T100I |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | In-System Programmable 3.3V Generic Digital CrosspointTM |
| 中文描述： | EE PLD, 9 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 5/27頁 |
| 文件大?。?/td> | 346K |
| 代理商： | ISPGDX80VA-9T100I |
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5
Specifications
ispGDX80VA
B10
B11
B12
B13
D6
D7
D8
D9
D10
D11
D12
D13
B6
B7
B8
B9
B12
B13
B14
B15
D8
D9
D10
D11
D8
D9
D10
D11
B4
B5
B6
B7
B11
B12
B13
B14
D7
D8
D9
D10
D9
D10
D11
D12
B5
B6
B7
B8
B9
B10
B11
B12
D5
D6
D7
D8
D11
D12
D13
D14
B7
B8
B9
B10
B8
B9
B10
B11
D4
D5
D6
D7
D12
D13
D14
D15
B8
B9
B10
B11
Data D/
MUXOUT
Data C/
MUXOUT
Data B/
MUXOUT
Data A/
MUXOUT
Reflected
I/O Cells
Normal
I/O Cells
Table 2. Adjacent I/O Cells (Mapping of
ispGDX80VA)
It can be seen from Figure 3 that if the D11 adjacent I/O
cell is used, the I/O group
“
A
”
input is no longer available
as a direct MUX input.
The ispGDXVA can implement MUXes up to 16 bits wide
in a single level of logic, but care must be taken when
combining adjacent I/O cell outputs with direct MUX
inputs. Any particular combination of adjacent I/O cells as
MUX inputs will dictate what I/O groups (A, B, C or D) can
be routed to the remaining inputs. By properly choosing
the adjacent I/O cells, all of the MUX inputs can be
utilized.
S0
S1
4 x 4
Crossbar
Switch
.m0
.m1
.m2
.m3
D13
I/O Group A
D11 MUX Out
I/O Group B
D12 MUX Out
I/O Group C
D14 MUX Out
I/O Group D
D15 MUX Out
ispGDX80VA I/O Cell
Figure 3. Adjacent I/O Cells vs. Direct Input Path for
ispGDX80VA, I/O D13
Special Features
Slew Rate Control
All output buffers contain a programmable slew rate
control that provides software-selectable slew rate op-
tions.
Open Drain Control
All output buffers provide a programmable Open-Drain
option which allows the user to drive system level reset,
interrupt and enable/disable lines directly without the
need for an off-chip Open-Drain or Open-Collector buffer.
Wire-OR logic functions can be performed at the printed
circuit board level.
Pull-up Resistor
All pins have a programmable active pull-up. A typical
resistor value for the pull-up ranges from 50k
to 80k
.
Output Latch (Bus Hold)
All pins have a programmable circuit that weakly holds
the previously driven state when all drivers connected to
the pin (including the pin's output driver as well as any
other devices connected to the pin by external bus) are
tristated.
User-Programmable I/Os
The ispGDX80VA features user-programmable
I/Os supporting either 3.3V or 2.5V output voltage level
options. The ispGDX80VA uses a VCCIO pin to provide
the 2.5V reference voltage when used.
PCI Compatible Drive Capability
The ispGDX80VA supports PCI compatible drive capa-
bility for all I/Os.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISPGDX80VA-9TN100I | 功能描述:模擬和數(shù)字交叉點 IC PROGRAMMABLE GEN DIG CROSSPOINT RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產品:Digital Crosspoint 封裝:Tube |
| ISPGDXTMFAMILY | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Generic Digital CrosspointTM |
| ISPHEADER01 | 制造商:Xeltek Inc 功能描述:ISP10/D10 |
| ISPICR1 | 功能描述:ADAPTER IN-CIRCUIT PROGRAMMING RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 配件 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program RoHS指令信息:IButton RoHS Compliance Plan 標準包裝:1 系列:- 附件類型:USB 至 1-Wire? RJ11 適配器 適用于相關產品:1-Wire? 設備 產品目錄頁面:1429 (CN2011-ZH PDF) |
| ISPL1048E-100LQ | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
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