參數資料
型號: ISP1362BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數: 69/150頁
文件大?。?/td> 647K
代理商: ISP1362BD
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
69 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
15. HC registers
The HC contains a set of on-chip control registers. These registers can be read or
written by the HC Driver (HCD). The Control and Status register set, the Frame
Counter register set and the Root Hub register set are grouped under the category of
HC operational registers (32 bits). These operational registers are made compatible
to Open Host Controller Interface (OpenHCI) operational registers. This enables the
OpenHCI HCD to be ported easily to the ISP1362.
Reserved bits may be de
fi
ned in future releases of this speci
fi
cation. To ensure
interoperability, the HCD that does not use a reserved
fi
eld must not assume that the
reserved
fi
eld contains logic 0. Furthermore, the HCD must always preserve the
values of the reserved
fi
eld. When a R/W register is modi
fi
ed, the HCD must
fi
rst read
the register, modify the desired bits and then write the register with the reserved bits
still containing the read value. Alternatively, the HCD can maintain an in-memory
copy of previously written values that can be modi
fi
ed and then written to the
HC register. When there is a write to set or clear the register, bits written to reserved
fi
elds must be logic 0.
As shown in
Table 34
, the offset locations (the commands for reading registers) of
these operational registers (32-bit registers) are similar to those de
fi
ned in the OHCI
speci
fi
cation. The addresses, however, are equal to offset divided by 4.
Table 34:
Command (Hex)
Read
00
01
02
03
04
05
0D
0E
0F
11
12
13
14
15
16
20
21
22
24
25
HC Control registers summary
Register
Write
N/A
HcRevision
81
HcControl
82
HcCommandStatus
83
HcInterruptStatus
84
HcInterruptEnable
85
HcInterruptDisable
8D
HcFmInterval
8E
HcFmRemaining
8F
HcFmNumber
91
HcLSThreshold
92
HcRhDescriptorA
93
HcRhDescriptorB
94
HcRhStatus
95
HcRhPortStatus[1]
96
HcRhPortStatus[2]
A0
HcHardwareCon
fi
guration
A1
HcDMACon
fi
guration
A2
HcTransferCounter
A4
Hc
μ
PInterrupt
A5
Hc
μ
PInterruptEnable
Width
Reference
Functionality
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
16
16
16
16
16
Section 15.1.1 on page 71
Section 15.1.2 on page 71
Section 15.1.3 on page 73
Section 15.1.4 on page 74
Section 15.1.5 on page 75
Section 15.1.6 on page 76
Section 15.2.1 on page 78
Section 15.2.2 on page 79
Section 15.2.3 on page 80
Section 15.2.4 on page 81
Section 15.3.1 on page 82
Section 15.3.2 on page 84
Section 15.3.3 on page 85
Section 15.3.4 on page 87
Section 15.3.4 on page 87
Section 15.4.1 on page 92
Section 15.4.2 on page 94
Section 15.4.3 on page 95
Section 15.4.4 on page 95
Section 15.4.5 on page 97
HC Control and Status
registers
HC Frame Counter
registers
HC Root Hub registers
HC DMA and Interrupt
Control registers
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