參數(shù)資料
型號: ISP1362BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 119/150頁
文件大?。?/td> 647K
代理商: ISP1362BD
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
119 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
16.1.8
Reset Device (F6H)
This command resets the DC in the same way as an external hardware reset by using
the input RESET. All registers are initialized to their
reset
values.
Code (Hex): F6
reset the device
Transaction
none (code only)
16.2 Data
fl
ow commands
Data
fl
ow commands are used to manage the data transmission between the USB
endpoints and the system microprocessor. Much of the data
fl
ow is initiated using an
interrupt to the microprocessor. The data
fl
ow commands are used to access the
endpoints and determine whether the endpoint buffer memory contains valid data.
Remark:
The IN buffer of an endpoint contains input data
for
the host. The OUT
buffer receives output data
from
the host.
16.2.1
Write or read Endpoint Buffer (R/W: 10H,12H
1FH/01H
0FH)
This command is used to access endpoint buffer memory for reading or writing. First,
the buffer pointer is reset to the beginning of the buffer. Following the command, a
maximum of (N
+
2) bytes can be written or read, N representing the size of the
endpoint buffer. For 16-bit access, the maximum number of words is (M + 1), with M
given by (N
+
1) divided by 2. After each read or write action, the buffer pointer is
automatically incremented by two.
In direct memory access (DMA), the
fi
rst two bytes or the
fi
rst word (the packet
length) are skipped: transfers start at the third byte or the second word of the
endpoint buffer. When reading, the DC can detect the last byte or word by using the
EOP condition. When writing to a bulk or interrupt endpoint, the endpoint buffer must
be completely
fi
lled before sending data to the host. Exception: when a DMA transfer
is stopped by an external EOT condition, the current buffer content (full or not) is sent
to the host.
Remark:
Reading data after a Write Endpoint Buffer command or writing data after a
Read Endpoint Buffer command data will cause unpredictable behavior of the DC.
Table 120: DcDMACounter register: bit allocation
Bit
15
Symbol
Reset
0
Access
R/W
Bit
7
Symbol
Reset
0
Access
R/W
14
13
12
DMACR[15:8]
0
R/W
4
DMACR[7:0]
0
R/W
11
10
9
8
0
0
0
0
0
0
R/W
6
R/W
5
R/W
3
R/W
2
R/W
1
R/W
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Table 121: DcDMACounter register: bit description
Bit
Symbol
15 to 0
DMACR[15:0]
Description
DcDMACounter register
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