參數(shù)資料
型號(hào): ISP1362BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 31/150頁
文件大?。?/td> 647K
代理商: ISP1362BD
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
31 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
To give a better view of the functionality,
Figure 15
shows a possible curve of V
CC
with
dips at t2
t3 and t4
t5. If the dip at t4
t5 is too short (that is,
<
11
μ
s), the internal
POR pulse will not react and will remain LOW. The internal POR starts with a HIGH at
t0. At t1, the detector will see the passing of the trip level and a delay element will add
another t
PORP
before it drops to LOW.
The internal POR pulse will be generated whenever V
CC
drops below V
trip
for more
than 11
μ
s.
The RESET pin can be either connected to V
CC
(using the internal POR circuit) or
externally controlled (by the micro, ASIC, and so on).
Figure 16
shows the availability
of the clock with respect to the external reset pulse.
11. On-The-Go (OTG) controller
11.1 Introduction
OTG is a supplement to the Hi-Speed USB (USB 2.0) speci
fi
cation that augments
existing USB peripherals by adding to these peripherals limited host capability to
support other targeted USB peripherals. It is primarily targeted at portable devices
because it addresses concerns related to such devices, such as a small connector
and low power. Non-portable devices (even standard hosts), nevertheless, can also
bene
fi
t from OTG features.
(1) PORP = power-on reset pulse.
Fig 15. Internal power-on reset timing.
Stable external clock is available at A.
Fig 16. Clock with respect to the external power-on reset.
004aaa482
VCC
t0
t1
t2
t3
t4
t5
Vtrip
tPORP
PORP(1)
tPORP
RESET
EXTERNAL CLOCK
A
004aaa484
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