參數(shù)資料
型號(hào): ISP1183BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Low-power Universal Serial Bus interface device with DMA
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC32
封裝: 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-617-1, HVQFN-32
文件頁(yè)數(shù): 37/62頁(yè)
文件大小: 295K
代理商: ISP1183BS
Philips Semiconductors
ISP1183
Low-power USB interface device with DMA
Product data
Rev. 01 — 24 February 2004
37 of 62
9397 750 11804
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
13.3.2
DMA Configuration register (R/W: F1H/F0H)
This command defines the DMA configuration of the ISP1183 and enables or
disables DMA transfers. The command accesses the DMA Configuration register,
which consists of 2 bytes. The bit allocation is given in
Table 32
. A bus reset will clear
bit DMAEN (DMA disabled), all other bits remain unchanged.
Code (hex): F0/F1 —
write or read DMA Configuration
Transaction —
write or read 2 bytes
[1]
Unchanged by a bus reset.
Table 31:
Bit
15
14 to 13
12 to 8
7 to 0
DMA Function and Scratch register: bit description
Symbol
Description
DMAEN
Writing logic 1 enables DMA function.
-
reserved; must be logic 0
SFIRH[4:0]
Scratch Information register (high byte)
SFIRL[7:0]
Scratch Information register (low byte)
Table 32:
Bit
Symbol
Reset
Access
Bit
Symbol
DMA Configuration register: bit allocation
15
14
CNTREN
SHORTP
0
[1]
0
[1]
R/W
R/W
7
6
13
12
11
10
9
8
reserved
0
[1]
R/W
5
0
[1]
R/W
4
0
[1]
R/W
3
DMA
START
0
R/W
0
[1]
R/W
2
0
[1]
R/W
1
0
[1]
R/W
0
EPDIX[3:0]
reserved
BURSTL[1:0]
Reset
Access
0
[1]
R/W
0
[1]
R/W
0
[1]
R/W
0
[1]
R/W
0
0
[1]
R/W
0
[1]
R/W
R/W
Table 33:
Bit
15
DMA Configuration register: bit description
Symbol
Description
CNTREN
Logic 1 enables the generation of an EOT condition, when the
DMA Counter register reaches zero. Bus reset value:
unchanged.
SHORTP
Logic 1 enables the short or empty packet mode. When
receiving (OUT endpoint) a short or empty packet, an EOT
condition is generated. When transmitting (IN endpoint), this bit
should be cleared. Bus reset value: unchanged.
-
reserved
EPDIX[3:0]
Indicates the destination endpoint for DMA, see
Table 7
.
14
13 to 8
7 to 4
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