參數(shù)資料
型號(hào): ISP1183BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Low-power Universal Serial Bus interface device with DMA
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC32
封裝: 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-617-1, HVQFN-32
文件頁數(shù): 26/62頁
文件大小: 295K
代理商: ISP1183BS
Philips Semiconductors
ISP1183
Low-power USB interface device with DMA
Product data
Rev. 01 — 24 February 2004
26 of 62
9397 750 11804
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Data flow commands
Write Control OUT Buffer
illegal: endpoint is
read-only
FIFO endpoint 0 IN
FIFO endpoints 1 to 14
(IN endpoints only)
(00)
-
Section 13.2.1 on page 32
Write Control IN Buffer
Write Endpoint n Buffer
(n = 1 to 14)
01
02 to 0F
N
64 bytes
isochronous:
N
1023 bytes
interrupt or bulk:
N
64 bytes
N
64 bytes
-
Read Control OUT Buffer
Read Control IN Buffer
FIFO endpoint 0 OUT
illegal: endpoint is
write-only
FIFO endpoints 1 to 14
(OUTendpoints only)
10
(11)
Read Endpoint n Buffer
(n = 1 to 14)
12 to 1F
isochronous:
N
1023 bytes
interrupt or bulk:
N
64 bytes
-
-
-
read 1 byte
Stall Control OUT Endpoint
Stall Control IN Endpoint
Stall Endpoint n (n = 1 to 14)
Read Control OUT Status
Endpoint 0 OUT
Endpoint 0 IN
Endpoints 1 to 14
Endpoint Status register
endpoint 0 OUT
Endpoint Status register
endpoint 0 IN
Endpoint Status register n
endpoints 1 to 14
illegal: IN endpoints
only
[1]
FIFO endpoint 0 IN
FIFO endpoints 1 to 14
(IN endpoints only)
[1]
FIFO endpoint 0 OUT
illegal
[2]
FIFO endpoints 1 to 14
(OUTendpoints only)
[2]
Endpoint 0 OUT
Endpoint 0 IN
Endpoints 1 to 14
Endpoint Status Image
register endpoint 0 OUT
Endpoint Status Image
register endpoint 0 IN
Endpoint Status Image
register n
endpoints 1 to 14
Endpoint 0 IN and OUT
40
41
42 to 4F
50
Section 13.2.3 on page 34
Section 13.2.2 on page 33
Read Control IN Status
51
read 1 byte
Read Endpoint n Status
(n = 1 to 14)
Validate Control OUT Buffer
52 to 5F
read 1 byte
(60)
-
Section 13.2.4 on page 34
Validate Control IN Buffer
Validate Endpoint n Buffer
(n = 1 to 14)
Clear Control OUT Buffer
Clear Control IN Buffer
Clear Endpoint n Buffer
(n = 1 to 14)
Unstall Control OUT Endpoint
Unstall Control IN Endpoint
Unstall Endpoint n (n = 1 to 14)
Check Control OUT Status
[3]
61
62 to 6F
-
-
70
(71)
72 to 7F
-
-
-
Section 13.2.5 on page 35
80
81
82 to 8F
D0
-
-
-
read 1 byte
Section 13.2.3 on page 34
Section 13.2.6 on page 35
Check Control IN Status
[3]
D1
read 1 byte
Check Endpoint n Status
(n = 1 to 14)
[3]
D2 to DF
read 1 byte
Acknowledge Setup
F4
-
Section 13.2.7 on page 36
Table 13:
Name
Command and register summary
…continued
Destination
Code
(hex)
Transaction
Reference
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