參數(shù)資料
型號: ISP1183BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Low-power Universal Serial Bus interface device with DMA
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC32
封裝: 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-617-1, HVQFN-32
文件頁數(shù): 34/62頁
文件大小: 295K
代理商: ISP1183BS
Philips Semiconductors
ISP1183
Low-power USB interface device with DMA
Product data
Rev. 01 — 24 February 2004
34 of 62
9397 750 11804
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
13.2.3
Stall or Unstall Endpoint (40H–4FH/80H–8FH)
These commands are used to stall or unstall an endpoint. The commands modify the
content of the Endpoint Status register (see
Table 26
).
A stalled control endpoint is automatically unstalled when it receives a SETUP token,
regardless of the packet content. If the endpoint should stay in its stalled state, the
microcontroller can restall it with the Stall Endpoint command.
When a stalled endpoint is unstalled (either by the Unstall Endpoint command or by
receiving a SETUP token), it is also reinitialized. This flushes the buffer: if it is an OUT
buffer, it waits for a DATA 0 PID; if it is an IN buffer, it writes a DATA 0 PID.
Code (hex): 40 to 4F —
stall (control OUT, control IN, endpoints 1 to 14)
Code (hex): 80 to 8F —
unstall (control OUT, control IN, endpoints 1 to 14)
Transaction —
none
Remark:
When unstalling a stalled endpoint, issue the unstall command two times.
The first unstall command will update the Endpoint Status register in RAM. The
second unstall command will reset the buffer pointers.
13.2.4
Validate Endpoint Buffer (61H–6FH)
This command signals the presence of valid data for transmission to the USB host, by
setting the Buffer Full flag of the selected IN endpoint. This indicates that the data in
the buffer is valid and can be sent to the host, when the next IN token is received. For
a double-buffered endpoint, this command switches the current FIFO for CPU
access.
Table 27:
Bit
7
Endpoint Status register: bit description
Symbol
Description
EPSTAL
This bit indicates whether the endpoint is stalled or not
(1 = stalled, 0 = not stalled).
Set by a Stall Endpoint command. Cleared by an Unstall
Endpoint command. The endpoint is automatically unstalled on
reception of a SETUP token.
EPFULL1
Logic 1 indicates that the secondary endpoint buffer is full.
EPFULL0
Logic 1 indicates that the primary endpoint buffer is full.
DATA_PID
This bit indicates the data PID of the next packet
(0 = DATA0 PID, 1 = DATA1 PID).
OVERWRITE
This bit is set by hardware. Logic 1 indicates that a new Setup
packet has overwritten the previous setup information, before it
was acknowledged or before the endpoint was stalled. This bit is
cleared by reading, if writing the setup data has finished.
Firmware must check this bit before sending an Acknowledge
Setup command or stalling the endpoint. On reading logic 1, the
firmware must stop ongoing setup actions and wait for a new
Setup packet.
SETUPT
Logic 1 indicates that the buffer contains a Setup packet.
CPUBUF
This bit indicates which buffer is currently selected for CPU
access (0 = primary buffer, 1 = secondary buffer).
-
reserved
6
5
4
3
2
1
0
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