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| 型號(hào)： | ISP1161A1BD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Universal Serial Bus single-chip host and device controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁(yè)數(shù)： | 13/127頁(yè) |
| 文件大小： | 2762K |
| 代理商： | ISP1161A1BD |
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Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
13 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
microprocessors can read or write ISP1161’s internal control registers and FIFO
buffer RAM through the parallel I/O (PIO) operating mode.
Figure 9
shows the parallel
I/O interface between a microprocessor and ISP1161.
8.2 DMA mode
ISP1161 also provides DMA mode for external microprocessors to access its internal
FIFO buffer RAM. Data can be transferred by DMA operation between a
microprocessor’s system memory and ISP1161’s internal FIFO buffer RAM. Note: the
DMA operation must be controlled by the external microprocessor system’s DMA
controller (Master).
Figure 10
shows the DMA interface between a microprocessor
system and ISP1161. ISP1161 provides two DMA channels: DMA channel 1
(controlled by DREQ1, DACK1 signals) is for the DMA transfer between a
microprocessor’s system memory and ISP1161 HC’s internal FIFO buffer RAM. DMA
channel 2 (controlled by DREQ2, DACK2 signals) is for the DMA transfer between a
microprocessor’s system memory and ISP1161 DC’s internal FIFO buffer RAM. The
EOT signal is an external end-of-transfer signal used to terminate the DMA transfer.
Some microprocessors may not have this signal. In this case, ISP1161 provides an
internal EOT signal to terminate the DMA transfer as well. Setting the
HcDMAConfiguration register (21H - Read, A1H - Write) enables ISP1161’s HC
internal DMA counter for DMA transfer. When the DMA counter reaches the value
that is set in the HcTransferCounter (22H - Read, A2H - Write) register to be used as
the byte count of the DMA transfer, the internal EOT signal will be generated to
terminate the DMA transfer.
Fig 9.
Parallel I/O interface between microprocessor and ISP1161.
MGT933
D[15:0]
RD
WR
CS
A2
IRQ2
MICRO-
PROCESSOR
ISP1161
D[15:0]
μ
P bus I/F
RD
WR
CS
A1
A1
IRQ1
A0
INT1
INT2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1161A1BD,118 | 功能描述:USB 接口集成電路 USB1.1 HOST &DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1161A1BD,151 | 功能描述:USB 接口集成電路 USB1.1 HOST &DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1161A1BD,157 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1161A1BDFA | 功能描述:IC USB HOST CONTROLLER 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1161A1BD-S | 功能描述:USB 接口集成電路 USB1.1 HOST &DEVICE CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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