參數(shù)資料
型號(hào): ISP1160BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Embedded Universal Serial Bus Host Controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 67/88頁
文件大?。?/td> 2044K
代理商: ISP1160BD
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 04 — 04 July 2003
67 of 88
9397 750 11371
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
The HCD must set the byte count into the HcTransferCounter register and check the
HcBufferStatus register before reading from or writing to the buffer. The HCD must
write the command (40H to read, C0H to write) once only, and then read or write both
bytes of the data word. After every read/write, the pointer of ITL buffer RAM will be
automatically increased by two to point to the next data word until it reaches the value
of the HcTransferCounter register; otherwise, an internal EOT signal is not generated
to set bit 2 (AllEOTInterrupt) of the Hc
μ
PInterrupt register and update the
HcBufferStatus register.
The HCD must take care of the fact that the internal buffer RAM is organized in bytes.
The HCD must write the byte count into the HcTransferCounter register, but the HCD
reads or writes the buffer RAM by 16 bits (by 1 word).
10.6.7
HcATLBufferPort register (R/W: 41H/C1H)
This is the ATL buffer RAM read/write port. Bits 15 to 8 contain the data byte that
comes from the Acknowledged Transfer List (ATL) buffer RAM’s odd address.
Bits 7 to 0 contain the data byte that comes from the ATL buffer RAM’s even address.
Code (Hex): 41 —
read
Code (Hex): C1 —
write
Table 62:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcITLBufferPort register: bit allocation
15
14
13
12
DataWord[15:8]
0
R/W
4
DataWord[7:0]
0
R/W
11
10
9
8
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
3
R/W
2
R/W
1
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 63:
Bit
15 to 0
HcITLBufferPort register: bit description
Symbol
DataWord[15:0]
Description
Read/write ITL buffer RAM’s two data bytes.
Table 64:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcATLBufferPort register: bit allocation
15
14
13
12
DataWord[15:8]
0
R/W
4
DataWord[7:0]
0
R/W
11
10
9
8
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
3
R/W
2
R/W
1
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 65:
Bit
15 to 0
HcATLBufferPort register: bit description
Symbol
DataWord[15:0]
Description
Read/write ATL buffer RAM’s two data bytes.
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