參數(shù)資料
型號: ISP1160
廠商: NXP Semiconductors N.V.
英文描述: Embedded Universal Serial Bus Host Controller
中文描述: 嵌入式通用串行總線主控制器
文件頁數(shù): 61/88頁
文件大?。?/td> 2044K
代理商: ISP1160
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 04 — 04 July 2003
61 of 88
9397 750 11371
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
10.4.5
Hc
μ
PInterruptEnable register (R/W: 25H/A5H)
The bits 6:0 in this register are the same as those in the Hc
μ
PInterrupt register. They
are used together with bit 0 of the HcHardwareConfiguration register to enable or
disable the bits in the Hc
μ
PInterrupt register.
On power-on, all bits in this register are masked with logic 0. This means no interrupt
request output on the interrupt pin INT can be generated.
When the bit is set to logic 1, the interrupt for the bit is not masked but enabled.
Code (Hex): 25 —
read
Code (Hex): A5 —
write
2
AllEOT
Interrupt
0 —
no event
1 —
implies that data transfer has been completed via PIO transfer
or DMA transfer. Occurrence of internal or external EOT will set
this bit.
0 —
no event
1
ATLInt
1 —
implies that the microprocessor must read ATL data from the
HC. This requires that the HcBufferStatus register must first be
read. The time for this interrupt depends on the number of clocks
bit set for USB activities in each ms.
0 —
no event
0
SOFITLInt
1 —
implies that SOF indicates the 1 ms mark. The ITL buffer that
the HC has handled must be read. To know the ITL buffer status,
the HcBufferStatus register must first be read. This is for the
microprocessor to get ISO data to or from the HC. For more
information, see the 6th paragraph in
Section 9.5
.
Table 43:
Bit
Hc
μ
PInterrupt register: bit description
…continued
Symbol
Description
Table 44:
Bit
Symbol
Reset
Access
Bit
Symbol
Hc
μ
PInterruptEnable register: bit allocation
15
14
13
12
11
10
9
8
reserved
0
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
HC
R/W
4
OPR
Interrupt
Enable
0
R/W
R/W
3
R/W
2
EOT
Interrupt
Enable
0
R/W
R/W
1
ATL
Interrupt
Enable
0
R/W
R/W
0
SOF
Interrupt
Enable
0
R/W
reserved
ClkReady
Suspended
Enable
0
R/W
reserved
Reset
Access
0
0
0
R/W
R/W
R/W
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