參數(shù)資料
型號(hào): ISP1160
廠商: NXP Semiconductors N.V.
英文描述: Embedded Universal Serial Bus Host Controller
中文描述: 嵌入式通用串行總線主控制器
文件頁數(shù): 58/88頁
文件大?。?/td> 2044K
代理商: ISP1160
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 04 — 04 July 2003
58 of 88
9397 750 11371
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
10.4.2
HcDMAConfiguration register (R/W: 21H/A1H)
Code (Hex): 21 —
read
Code (Hex): A1 —
write
2
InterruptOutputPolarity
0 —
active LOW
1 —
active HIGH
0 —
interrupt is level-triggered
1
InterruptPinTrigger
1 —
interrupt is edge-triggered
This bit is used as pin INT’s master interrupt enable and
should be used together with register
Hc
μ
PInterruptEnable to enable pin INT.
0
InterruptPinEnable
0 —
pin INT is disabled
1 —
pin INT is enabled
Table 37:
Bit
HcHardwareConfiguration register: bit description
…continued
Symbol
Description
Table 38:
Bit
Symbol
Reset
Access
Bit
Symbol
HcDMAConfiguration register: bit allocation
15
14
13
12
11
10
9
8
reserved
0
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
4
DMA
Enable
R/W
3
R/W
2
DMA
Counter
Select
0
R/W
R/W
1
R/W
0
reserved
BurstLen[1:0]
reserved
ITL_ATL_
DataSelect
DMARead
WriteSelect
Reset
Access
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 39:
Bit
15 to 7
6 to 5
HcDMAConfiguration register: bit description
Symbol
Description
-
reserved
BurstLen[1:0]
00 —
single-cycle burst DMA
01 —
4-cycle burst DMA
10 —
8-cycle burst DMA
11 —
reserved
0 —
DMA is terminated
4
DMAEnable
1 —
DMA is enabled
This bit will be reset to logic 0 when DMA transfer is completed.
reserved
3
-
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