參數(shù)資料
型號(hào)： ISP1130N
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Universal Serial Bus compound hub with integrated keyboard controller
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDIP56
封裝： PLASTIC, SDIP-56
文件頁數(shù)： 48/68頁
文件大?。?/td> 1786K
代理商： ISP1130N
Philips Semiconductors
ISP1130
USB compound hub with keyboard controller
Objective specification
Rev. 01 — 23 March 2000
48 of 68
9397 750 06895
Philips Electronics N.V. 2000. All rights reserved.
11.3 Data transfer
The I
2
C-bus interface can be used to read configuration data from an external
EEPROM, e.g. upon a hardware or USB bus reset. The EEPROM must be enabled
and disabled using output pin MEMSEL/UPGL. To select the I
2
C-bus function of pins
MX3/SCL and MX4/SDA, bit ENS1 in the I2C0CON register must be set to logic 1.
The number and the organization of the data bytes read from the EEPROM can be
determined by the firmware designer.
The I
2
C-bus interface is accessed via a number of SFRs, shown in
Table 75
.
Table 75: I
2
C register addresses
Register
SFR address
I2C0CON
D8H
I2C0STA
D9H
I2C0DAT
DAH
I2C0ADR
DBH
Description
I
2
C-bus control register
I
2
C-bus status register
I
2
C-bus data register
I
2
C-bus address register
Table 76: I2C0CON register: bit allocation
Bit
7
Symbol
CR2
Reset
0
Access
R/W
6
5
4
3
SI
0
2
1
0
ENS1
0
R/W
STA
0
R/W
STO
0
R/W
AA
0
R/W
CR1
0
R/W
CR0
0
R/W
R/W
Table 77: I2C0CON register: bit description
Bit
[1]
Symbol
I2C0CON.7
CR2
I2C0CON.6
ENS1
Description
selects I
2
C-bus bit frequency in Master mode, see
Table 78
Enable Serial I/O
. A logic 1 enables the I
2
C-bus interface
and sets pins MX3/SCL and MX4/SDA to logic 1. A logic 0
disables the I
2
C-bus interface and clears bit STO to logic 0,
allowing MX3/SCL and MX4/SDA to be used as open drain
I/O pins.
START flag
. In Slave mode a logic 1 generates a START
condition as soon as the bus is free. In Master mode a
logic 1 generates a repeated START condition.
STOP flag
. In maSter mode a logic 1 generates a STOP
condition. This bit is cleared by hardware if a STOP
condition is detected on the bus. In Slave mode a logic 1 can
be used to recover from an error: it causes SDA and SCL to
be released and the device to be unaddressed.
Serial Interrupt flag
. A logic 1 signals a valid status change
(see
Table 83
), causing the SCL LOW period to be stretched
and the transfer to be suspended. This bit must be cleared
by software when servicing the interrupt.
I2C0CON.5
STA
I2C0CON.4
STO
I2C0CON.3
SI
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