參數(shù)資料
型號： ISP1130N
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Universal Serial Bus compound hub with integrated keyboard controller
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDIP56
封裝： PLASTIC, SDIP-56
文件頁數(shù)： 39/68頁
文件大?。?/td> 1786K
代理商： ISP1130N
Philips Semiconductors
ISP1130
USB compound hub with keyboard controller
Objective specification
Rev. 01 — 23 March 2000
39 of 68
9397 750 06895
Philips Electronics N.V. 2000. All rights reserved.
10.4 Hub control registers
The hub control registers (Command and Data) are mapped to the external data
memory space of the 80C51 as shown in
Table 57
. To access these registers use a
MOVX instruction.
10.5 Interrupt structure
The ISP1130 implements a 6-source interrupt structure with 2 priority levels. The
interrupt vector addresses and polling sequence is given in
Table 58
. The interrupt
priority levels are set via the Interrupt Polarity (IP) register (see
Table 61
) and the
interrupts can be enabled or disabled via the Interrupt Enable (IE) register (see
Table 59
).
External interrupt 0 (EX0) is generated by the USB core when an activity occurs for
any of the three embedded functions. Interrupt EX0 is level-triggered and sets bit IE0
in the TCON register. IE0 is cleared by hardware when the service routine is entered.
External interrupt 1 (EX1) is generated by a key press in the matrix. Interrupt EX1 is
level-triggered and sets bit IE1 in the TCON register. IE1 is cleared by hardware
when the service routine is entered. When the device is in ‘suspend’ state (the
microcontroller clock is disabled), interrupt EX1 is registered and an internal Remote
Wakeup is generated to restart the PLL and the clocks. When the device resumes its
function and the clock to microcontroller core has been restored, the firmware
branches to the interrupt service routine for EX1.
External interrupt 2 (IN2) is generated by input pin INT, which is edge-triggered
(HIGH-to-LOW transition).
Timer 0 and Timer 1 interrupts are generated by a timer register overflow (except for
Timer 0 in Mode 3), signalled by bits TF0 and TF1 in the TCON register. The bit that
generated the interrupt is cleared by hardware, when the service routine is entered.
Table 57: Hub control registers: address mapping
Register
Command
Data
Access
write
read/write
Address (Hex)
FFFE
FFFF
Table 58: Interrupt vectors and polling sequence
Source
Description
EX0
external 0 interrupt (USB)
ET0
timer 0 interrupt
EX1
external 1 interrupt (keyboard)
ET1
timer 1 interrupt
I2C
I
2
C-bus interrupt
IN2
external 2 interrupt (input INT)
Vector address
0003H
000BH
0013H
001BH
0023H
002BH
相關(guān)PDF資料
PDF描述
ISP1160 Embedded Universal Serial Bus Host Controller
ISP1160BD Embedded Universal Serial Bus Host Controller
ISP1160BM Embedded Universal Serial Bus Host Controller
ISP1161A Full-speed Universal Serial Bus single-chip host and device controller
ISP1161ABD Full-speed Universal Serial Bus single-chip host and device controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1160 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Embedded Universal Serial Bus Host Controller
ISP1160BD 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Embedded Universal Serial Bus Host Controller
ISP1160BD,157 功能描述:USB 接口集成電路 USB 1.1 HOST CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1160BD/01 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Embedded Universal Serial Bus Host Controller
ISP1160BD/01,118 功能描述:USB 接口集成電路 USB HOST CTRL RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*