參數(shù)資料
型號(hào)： ISP1130N
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Universal Serial Bus compound hub with integrated keyboard controller
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDIP56
封裝： PLASTIC, SDIP-56
文件頁(yè)數(shù)： 42/68頁(yè)
文件大?。?/td> 1786K
代理商： ISP1130N
Philips Semiconductors
ISP1130
USB compound hub with keyboard controller
Objective specification
Rev. 01 — 23 March 2000
42 of 68
9397 750 06895
Philips Electronics N.V. 2000. All rights reserved.
[1]
All bits are individually addressable.
10.7 Watchdog timer
The Watchdog timer is a counter that resets the microcontroller upon overflow. This
allows recovery from erroneous processor states (e.g. caused by electrical noise or
RF-interference). To prevent the Watchdog timer from overflowing, the software must
reload the counter within a predefined (programmable) time.
The Watchdog timer is a 19-bit counter, consisting of an 11-bit prescaler and an 8-bit
SFR (WDT). The counter is clocked in state 2 of every CPU cycle (= 6 clocks) and
generates a reset when register WDT overflows. For a 12 MHz clock frequency, the
interval between overflows can be programmed between 1.024 ms (WDT = FFH) and
262.144 ms (WDT = 00H). After a reset the WDT register contains all zeroes.
To enable loading of the Watchdog timer, bit WLE in the PCON register must be set to
logic 1 (see
Table 51
). When this is done for the first time, it also starts the timer. The
Watchdog timer can be disabled by writing 55H to the WDTKEY register, or by a
hardware reset.
Table 67: TCON register: bit allocation
Bit
7
Symbol
TF1
Reset
0
Access
R
6
5
4
3
2
1
0
TR1
0
R/W
TF0
0
R
TR0
0
R/W
IE1
0
R
IT1
0
R/W
IE0
0
R
IT0
0
R/W
Table 68: TCON register: bit description
Bit
[1]
Symbol
TCON.7
TF1
Description
Timer 1 overflow flag; set by hardware upon Timer 1 overflow;
cleared by hardware upon entering the interrupt service routine
Timer 1 run control bit; 0 = timer OFF, 1 = timer ON
Timer 0 overflow flag; set by hardware upon Timer 0 overflow;
cleared by hardware upon entering the interrupt service routine
Timer 0 run control bit; 0 = timer OFF, 1 = timer ON
external interrupt 1 flag; set by hardware when a keyboard
interrupt is detected; cleared by hardware upon entering the
interrupt service routine
triggering mode for external interrupt 1, set by software;
must always be logic 0 (= HIGH-to-LOW transition)
external interrupt 0 flag; set by hardware when a USB core
interrupt is detected; cleared by hardware upon entering the
interrupt service routine
triggering mode for external interrupt 0, set by software;
must always be 0 (= HIGH-to-LOW transition)
TCON.6
TCON.5
TR1
TF0
TCON.4
TCON.3
TR0
IE1
TCON.2
IT1
TCON.1
IE0
TCON.0
IT0
Table 69: Watchdog timer registers: address mapping
Register
WDTKEY
WDT
Access
write
write
Address (Hex)
FE
FF
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