參數(shù)資料
型號(hào)： ISL6580CR
廠商： INTERSIL CORP
元件分類(lèi)： 穩(wěn)壓器
英文描述： Integrated Power Stage
中文描述： 35 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PQCC56
封裝： 8 X 8 MM, PLASTIC, QFN-56
文件頁(yè)數(shù)： 27/31頁(yè)
文件大?。?/td> 1391K
代理商： ISL6580CR
27
contributions from the ESR and the ESL of the output
capacitor can be substantial, as expressed below:
(
V
L
in
where
D
V is the output voltage ripple, V
IN
is the input
voltage, V
out
is the output voltage, f
sw
is the power stage
switching frequency, and L is the effective output
inductance. The contributions of ESR and ESL of the output
capacitor to the output voltage ripple are illustrated in
Figure 44.
For instance, a 4-phase VRM operating from a 12V input at
500kHz with 400nH inductance per phase and delivering
1.4V output will approximately have a fundamental ripple of
25 mV when the output capacitor has an effective ESR and
ESL or 0.5mW and 0.1nH respectively. Even though
OSCON capacitors are much better than ordinary electrolytic
capacitors, their ESR and ESL values are high enough to
result in substantial steady-state ripple. Consequently
several OSCON capacitors are connected in parallel at the
output to minimize the ESL and ESR effects.
Transient Response
The choice of output capacitance also impacts the transient
performance of the voltage regulator. Immediately following
a load current step, the output capacitor bank provides
charge to the load until the feedback loop catches up. As the
capacitor charge drains (low-high load step) or accumulates
(high-low load step), the output voltage also varies
accordingly. Considering that it is easier to charge or
discharge low capacitance, higher capacitance values are
desired to minimize the excursion of the load voltage. It is
possible to choose the number of OSCON capacitors that
will provide a transient response with negligible voltage
overshoot or droop. Systems that have feedback loops with
higher crossover frequency require smaller output
capacitance.
Start-Up
It is well established that several OSCON capacitors can be
connected in parallel to improve the voltage ripple and
transient voltage excursion. However, this results in an area
penalty to accommodate the capacitor count on the board. In
addition, the inrush current requirement at start-up goes up
with an increase in the effective output capacitance value.
The state control on the VRM has a soft-start mechanism
that ensures that the output voltage does not overshoot
beyond the set point at start-up. However, the lowest
regulated output voltage of the system is around 0.7V and
the system operates in an open loop manner until the error
voltage is within the span of the voltage A/D converter.
During this time, the duty cycle of the PWM signal expands
at a rate determined by the compensator. Systems with high
output capacitance take more time to raise the output
voltage to the minimum voltage necessary for regulation.
The current supported by each channel increases in
proportion to the increase in duty cycle. The VRM has an in-
built over-current protection mechanism that detects
conditions of high-current flow through the entire system as
well as individual channels. Beyond a threshold level, the
inrush current can be interpreted as an overload condition,
causing the system to shut down. It is possible to avoid this
condition by reducing the pulse-by-pulse trip level. However,
this mode of operation is not recommended because it
deteriorates the transient performance of the system during
a low to high load current step. A better approach is to avoid
overpopulating the output stage with OSCON capacitors.
As an alternative to using several OSCON capacitors,
ceramic capacitors are normally connected in parallel with
the output OSCON capacitors to improve the high-frequency
response of the system. Ceramic capacitors have much
lower ESR and ESL compared to OSCONs. This enables
them to absorb short-duration phenomena such as glitches
better than OSCONs. When the switching frequency of the
power stage exceeds 500kHz, more ceramic capacitors are
needed to limit the transient glitches.
Max Gate Drive
Excessive RMS current in the lower gate drive pins can
reduce the reliability of ISL6580. Gate drive current depends
on V
DRIVE
, switching frequency and the capacitance of the
lower side FET. Below is a graph of the maximum reliable
gate capacitance as a function of switching frequency and
V
DRIVE
. Gate capacitance is usually listed in the MOSFET
data sheet as Ciss. If Ciss is not specified it can be
)
L
ESR
f
V
V
V
ESL
V
V
sw
out
out
in
in
+
≈
(EQ. 17)
V
V
ESL
V
ESR
FIGURE 44. CONTRIBUTIONS OF ESR AND ESL OF OUTPUT
CAPACITOR TO OUTPUT VOLTAGE RIPPLE
ISL6580
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